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legup-4.0
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legup-4.0
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#include <PPCISelLowering.h>
Inheritance diagram for llvm::PPCTargetLowering:Public Member Functions | |
| PPCTargetLowering (PPCTargetMachine &TM) | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| MVT | getScalarShiftAmountTy (EVT LHSTy) const override |
| EVT | getSetCCResultType (LLVMContext &Context, EVT VT) const override |
| getSetCCResultType - Return the ISD::SETCC ValueType More... | |
| bool | getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override |
| bool | SelectAddressRegReg (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const |
| bool | SelectAddressRegImm (SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const |
| bool | SelectAddressRegRegOnly (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const |
| Sched::Preference | getSchedulingPreference (SDNode *N) const override |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| void | ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| unsigned | getRegisterByName (const char *RegName, EVT VT) const override |
| void | computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override |
| MachineBasicBlock * | EmitAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is64Bit, unsigned BinOpcode) const |
| MachineBasicBlock * | EmitPartwordAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode) const |
| MachineBasicBlock * | emitEHSjLjSetJmp (MachineInstr *MI, MachineBasicBlock *MBB) const |
| MachineBasicBlock * | emitEHSjLjLongJmp (MachineInstr *MI, MachineBasicBlock *MBB) const |
| ConstraintType | getConstraintType (const std::string &Constraint) const override |
| ConstraintWeight | getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override |
| std::pair< unsigned, const TargetRegisterClass * > | getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const override |
| unsigned | getByValTypeAlignment (Type *Ty) const override |
| void | LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override |
| bool | isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override |
| bool | isLegalICmpImmediate (int64_t Imm) const override |
| bool | isLegalAddImmediate (int64_t Imm) const override |
| bool | isTruncateFree (Type *Ty1, Type *Ty2) const override |
| bool | isTruncateFree (EVT VT1, EVT VT2) const override |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Returns true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override |
| EVT | getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override |
| bool | allowsUnalignedMemoryAccesses (EVT VT, unsigned AddrSpace, bool *Fast=nullptr) const override |
| bool | isFMAFasterThanFMulAndFAdd (EVT VT) const override |
| bool | shouldExpandBuildVectorWithShuffles (EVT VT, unsigned DefinedValues) const override |
| FastISel * | createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override |
| bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override |
| Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv. More... | |
| virtual bool | getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| virtual unsigned | getJumpTableEncoding () const |
| virtual const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const |
| virtual SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const |
| Returns relocation base for the given PIC jumptable. More... | |
| virtual const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const |
| Returns a pair of (return value, chain). More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| virtual unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const |
| bool | isConstTrueVal (const SDNode *N) const |
| bool | isConstFalseVal (const SDNode *N) const |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const |
| virtual bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const |
| virtual bool | isDesirableToCommuteWithShift (const SDNode *N) const |
| Return true if it is profitable to move a following shift through this. More... | |
| virtual bool | isTypeDesirableForOp (unsigned, EVT VT) const |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| virtual bool | IsDesirableToPromoteOp (SDValue, EVT &) const |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| virtual void | HandleByVal (CCState *, unsigned &, unsigned) const |
| Target-specific cleanup for formal ByVal parameters. More... | |
| virtual bool | isUsedByReturnOnly (SDNode *, SDValue &) const |
| virtual bool | mayBeEmittedAsTailCall (CallInst *) const |
| virtual const char * | getClearCacheBuiltinName () const |
| virtual MVT | getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const |
| virtual const MCPhysReg * | getScratchRegisters (CallingConv::ID CC) const |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const |
| virtual void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual bool | ExpandInlineAsm (CallInst *) const |
| virtual AsmOperandInfoVector | ParseConstraints (ImmutableCallSite CS) const |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| virtual const char * | LowerXConstraint (EVT ConstraintVT) const |
| SDValue | BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const |
| Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More... | |
| SDValue | BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More... | |
| SDValue | BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More... | |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| virtual void | AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const |
| const TargetMachine & | getTargetMachine () const |
| const DataLayout * | getDataLayout () const |
| const TargetLoweringObjectFile & | getObjFileLowering () const |
| bool | isBigEndian () const |
| bool | isLittleEndian () const |
| virtual MVT | getPointerTy (uint32_t=0) const |
| unsigned | getPointerSizeInBits (uint32_t AS=0) const |
| unsigned | getPointerTypeSizeInBits (Type *Ty) const |
| EVT | getShiftAmountTy (EVT LHSTy) const |
| virtual MVT | getVectorIdxTy () const |
| bool | isSelectExpensive () const |
| Return true if the select operation is expensive for this target. More... | |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (EVT VT) const |
| Return the preferred vector type legalization action. More... | |
| bool | isIntDivCheap () const |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| bool | isPow2DivCheap () const |
| Return true if pow2 div is cheaper than a chain of srl/add/sra. More... | |
| bool | isJumpExpensive () const |
| bool | isPredictableSelectExpensive () const |
| virtual bool | isLoadBitCastBeneficial (EVT, EVT) const |
| bool | isMaskAndBranchFoldingLegal () const |
| Return if the target supports combining a chain like: More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT) const |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| bool | isTypeLegal (EVT VT) const |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| virtual bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const |
| virtual bool | isFPImmLegal (const APFloat &, EVT) const |
| virtual bool | isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| virtual bool | isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, MVT VT) const |
| bool | isLoadExtLegal (unsigned ExtType, EVT VT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| LegalizeAction | getTruncStoreAction (MVT ValVT, MVT MemVT) const |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| EVT | getValueType (Type *Ty, bool AllowUnknown=false) const |
| MVT | getSimpleValueType (Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| virtual bool | ShouldShrinkFPConstant (EVT) const |
| bool | hasBigEndianPartOrdering (EVT VT) const |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| virtual bool | isSafeMemOpType (MVT) const |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| bool | supportJumpTables () const |
| Return whether the target can generate code for jump tables. More... | |
| int | getMinimumJumpTableEntries () const |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| unsigned | getExceptionPointerRegister () const |
| unsigned | getExceptionSelectorRegister () const |
| unsigned | getJumpBufSize () const |
| unsigned | getJumpBufAlignment () const |
| unsigned | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| unsigned | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| unsigned | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| unsigned | getPrefLoopAlignment () const |
| Return the preferred loop alignment. More... | |
| bool | getInsertFencesForAtomic () const |
| virtual bool | getStackCookieLocation (unsigned &, unsigned &) const |
| virtual unsigned | getMaximalGlobalOffset () const |
| virtual bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
Helpers for TargetTransformInfo implementations | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< unsigned, MVT > | getTypeLegalizationCost (Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
Static Public Member Functions | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
Protected Member Functions | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
Private Attributes | |
| const PPCSubtarget & | Subtarget |
Helpers for load-linked/store-conditional atomic expansion. | |
| virtual Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const |
| virtual Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| virtual bool | shouldExpandAtomicInIR (Instruction *Inst) const |
| virtual void | resetOperationActions () |
| Reset the operation actions based on target options. More... | |
| virtual bool | GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const |
| virtual int | getScalingFactorCost (const AddrMode &AM, Type *Ty) const |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| virtual bool | allowTruncateForTailCall (Type *, Type *) const |
| virtual bool | isZExtFree (Type *, Type *) const |
| virtual bool | isZExtFree (EVT, EVT) const |
| Reset the operation actions based on target options. More... | |
| virtual bool | isZExtFree (SDValue Val, EVT VT2) const |
| virtual bool | hasPairedLoad (Type *, unsigned &) const |
| virtual bool | hasPairedLoad (EVT, unsigned &) const |
| Specify maximum number of store instructions per memset call. More... | |
| virtual bool | isFNegFree (EVT VT) const |
| virtual bool | isFAbsFree (EVT VT) const |
| virtual bool | isNarrowingProfitable (EVT, EVT) const |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| LegalizeKind | getTypeConversion (LLVMContext &Context, EVT VT) const |
| Reset the operation actions based on target options. More... | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum bytes of store instructions per memcpy call. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| unsigned | MaxStoresPerMemmove |
| Specify maximum bytes of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| bool | PredictableSelectIsExpensive |
| bool | MaskAndBranchFoldingIsLegal |
| void | setBooleanContents (BooleanContent Ty) |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| void | setBooleanVectorContents (BooleanContent Ty) |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| void | setUseUnderscoreLongJmp (bool Val) |
| void | setSupportJumpTables (bool Val) |
| Indicate whether the target can generate code for jump tables. More... | |
| void | setMinimumJumpTableEntries (int Val) |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| void | setExceptionPointerRegister (unsigned R) |
| void | setExceptionSelectorRegister (unsigned R) |
| void | setSelectIsExpensive (bool isExpensive=true) |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| void | setJumpIsExpensive (bool isExpensive=true) |
| void | setIntDivIsCheap (bool isCheap=true) |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | setPow2DivIsCheap (bool isCheap=true) |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| void | clearRegisterClasses () |
| Remove all register classes. More... | |
| void | clearOperationActions () |
| Remove all operation actions. More... | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (MVT VT) const |
| void | computeRegisterProperties () |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| void | setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action) |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| void | setJumpBufSize (unsigned Size) |
| Set the target's required jmp_buf buffer size (in bytes); default is 200. More... | |
| void | setJumpBufAlignment (unsigned Align) |
| void | setMinFunctionAlignment (unsigned Align) |
| Set the target's minimum function alignment (in log2(bytes)) More... | |
| void | setPrefFunctionAlignment (unsigned Align) |
| void | setPrefLoopAlignment (unsigned Align) |
| void | setMinStackArgumentAlignment (unsigned Align) |
| Set the minimum stack alignment of an argument (in log2(bytes)). More... | |
| void | setInsertFencesForAtomic (bool fence) |
| bool | isLegalRC (const TargetRegisterClass *RC) const |
| MachineBasicBlock * | emitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const |
Definition at line 344 of file PPCISelLowering.h.
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inherited |
Definition at line 2126 of file TargetLowering.h.
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inherited |
Definition at line 2484 of file TargetLowering.h.
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inherited |
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
Definition at line 106 of file TargetLowering.h.
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inherited |
Enum that describes how the target represents true/false values.
| Enumerator | |
|---|---|
| UndefinedBooleanContent | |
| ZeroOrOneBooleanContent | |
| ZeroOrNegativeOneBooleanContent | |
Definition at line 109 of file TargetLowering.h.
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inherited |
| Enumerator | |
|---|---|
| C_Register | |
| C_RegisterClass | |
| C_Memory | |
| C_Other | |
| C_Unknown | |
Definition at line 2425 of file TargetLowering.h.
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inherited |
| Enumerator | |
|---|---|
| CW_Invalid | |
| CW_Okay | |
| CW_Good | |
| CW_Better | |
| CW_Best | |
| CW_SpecificReg | |
| CW_Register | |
| CW_Memory | |
| CW_Constant | |
| CW_Default | |
Definition at line 2433 of file TargetLowering.h.
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inherited |
This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| Legal | |
| Promote | |
| Expand | |
| Custom | |
Definition at line 84 of file TargetLowering.h.
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inherited |
This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| TypeLegal | |
| TypePromoteInteger | |
| TypeExpandInteger | |
| TypeSoftenFloat | |
| TypeExpandFloat | |
| TypeScalarizeVector | |
| TypeSplitVector | |
| TypeWidenVector | |
Definition at line 93 of file TargetLowering.h.
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inherited |
Enum that describes what type of support for selects the target has.
| Enumerator | |
|---|---|
| ScalarValSelect | |
| ScalarCondVectorVal | |
| VectorMaskSelect | |
Definition at line 116 of file TargetLowering.h.
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explicit |
Definition at line 63 of file PPCISelLowering.cpp.
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inlineprotectedinherited |
Tells the code generator which bitwidths to bypass.
Definition at line 1063 of file TargetLowering.h.
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inlineprotectedinherited |
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.
Definition at line 1173 of file TargetLowering.h.
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inlineprotectedinherited |
Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.
Definition at line 1074 of file TargetLowering.h.
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virtualinherited |
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.
Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.
Definition at line 325 of file SelectionDAGISel.cpp.
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overridevirtual |
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9205 of file PPCISelLowering.cpp.
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inlinevirtualinherited |
Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1311 of file TargetLowering.h.
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inherited |
Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.
Definition at line 2617 of file TargetLowering.cpp.
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inherited |
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html
Definition at line 2646 of file TargetLowering.cpp.
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inherited |
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html
Definition at line 2705 of file TargetLowering.cpp.
|
overrideprivatevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 5016 of file PPCISelLowering.cpp.
|
virtualinherited |
Returns true if the operation can trap for the value type.
VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.
canOpTrap - Returns true if the operation can trap for the value type. VT must be a legal type.
Definition at line 869 of file TargetLoweringBase.cpp.
|
inlineprotectedinherited |
|
inlineprotectedinherited |
Remove all register classes.
Definition at line 1081 of file TargetLowering.h.
|
virtualinherited |
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.
ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
Definition at line 2582 of file TargetLowering.cpp.
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 8764 of file PPCISelLowering.cpp.
|
virtualinherited |
This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.
ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1104 of file TargetLowering.cpp.
|
protectedinherited |
Once all of the register classes are added, this allows us to compute derived properties we expose.
computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition at line 1025 of file TargetLoweringBase.cpp.
|
overridevirtual |
createFastISel - This method returns a target-specific FastISel object, or null if the target does not support "fast" instruction selection.
Reimplemented from llvm::TargetLowering.
Definition at line 9273 of file PPCISelLowering.cpp.
|
private |
Definition at line 4130 of file PPCISelLowering.cpp.
|
private |
Definition at line 7927 of file PPCISelLowering.cpp.
|
private |
Definition at line 7405 of file PPCISelLowering.cpp.
|
private |
Definition at line 7468 of file PPCISelLowering.cpp.
|
private |
Definition at line 7648 of file PPCISelLowering.cpp.
| MachineBasicBlock * PPCTargetLowering::EmitAtomicBinary | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB, | ||
| bool | is64Bit, | ||
| unsigned | BinOpcode | ||
| ) | const |
Definition at line 6524 of file PPCISelLowering.cpp.
| MachineBasicBlock * PPCTargetLowering::emitEHSjLjLongJmp | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const |
Definition at line 6862 of file PPCISelLowering.cpp.
| llvm::MachineBasicBlock * PPCTargetLowering::emitEHSjLjSetJmp | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const |
Definition at line 6714 of file PPCISelLowering.cpp.
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 6967 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 932 of file TargetLowering.h.
| MachineBasicBlock * PPCTargetLowering::EmitPartwordAtomicBinary | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB, | ||
| bool | is8bit, | ||
| unsigned | Opcode | ||
| ) | const |
Definition at line 6584 of file PPCISelLowering.cpp.
|
protectedinherited |
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
Definition at line 946 of file TargetLoweringBase.cpp.
|
inlinevirtualinherited |
Perform a store-conditional operation to Addr. Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 939 of file TargetLowering.h.
|
private |
EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address stack slot. Returns the chain as result and the loaded frame pointers in LROpOut/FPOpout. Used when tail calling.
Definition at line 3426 of file PPCISelLowering.cpp.
|
inherited |
Expand float(f32) to SINT(i64) conversion
| N | Node to expand |
| Result | output after conversion |
Definition at line 2889 of file TargetLowering.cpp.
|
inlinevirtualinherited |
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 2421 of file TargetLowering.h.
|
inherited |
Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.
| HiLoVT | The value type to use for the Lo and Hi nodes. |
| LL | Low bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS. |
| LH | High bits of the LHS of the MUL. See LL for meaning. |
| RL | Low bits of the RHS of the MUL. See LL for meaning |
| RH | High bits of the RHS of the MUL. See LL for meaning. |
Definition at line 2786 of file TargetLowering.cpp.
|
private |
Definition at line 2545 of file PPCISelLowering.cpp.
|
protectedvirtualinherited |
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.
Definition at line 998 of file TargetLoweringBase.cpp.
|
private |
Definition at line 3767 of file PPCISelLowering.cpp.
|
inlineoverridevirtual |
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv.
Reimplemented from llvm::TargetLowering.
Definition at line 516 of file PPCISelLowering.h.
|
inlinevirtualinherited |
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.
Definition at line 1236 of file TargetLowering.h.
|
inlineinherited |
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.
"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.
Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.
Definition at line 290 of file TargetLowering.h.
|
inlineinherited |
Definition at line 296 of file TargetLowering.h.
|
inlineinherited |
Returns map of slow types for division or remainder with corresponding fast types
Definition at line 222 of file TargetLowering.h.
|
overridevirtual |
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 746 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call
Reimplemented in llvm::X86TargetLowering.
Definition at line 2310 of file TargetLowering.h.
|
inlineinherited |
Get the CondCode that's to be used to test the result of the comparison libcall against zero.
Definition at line 1437 of file TargetLowering.h.
|
virtualinherited |
Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.
Definition at line 1214 of file TargetLoweringBase.cpp.
|
inlineinherited |
Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 589 of file TargetLowering.h.
|
overridevirtual |
getConstraintType - Given a constraint, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 8805 of file PPCISelLowering.cpp.
|
inlineinherited |
Definition at line 150 of file TargetLowering.h.
|
inlineinherited |
If a physical register, this returns the register that receives the exception address on entry to a landing pad.
Definition at line 845 of file TargetLowering.h.
|
inlineinherited |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Definition at line 851 of file TargetLowering.h.
|
inlinestaticinherited |
Definition at line 124 of file TargetLowering.h.
|
private |
Definition at line 5133 of file PPCISelLowering.cpp.
|
inlineinherited |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 553 of file TargetLowering.h.
|
inlineinherited |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 571 of file TargetLowering.h.
|
inlineinherited |
Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.
Definition at line 889 of file TargetLowering.h.
|
inlineinherited |
Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)
Definition at line 863 of file TargetLowering.h.
|
inlineinherited |
Returns the target's jmp_buf size in bytes (if never set, the default is 200)
Definition at line 857 of file TargetLowering.h.
|
virtualinherited |
Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
Reimplemented in llvm::MipsTargetLowering, llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::XCoreTargetLowering.
Definition at line 222 of file TargetLowering.cpp.
|
inlineinherited |
Get the CallingConv that should be used for the specified libcall.
Definition at line 1447 of file TargetLowering.h.
|
inlineinherited |
Get the libcall routine name for the specified libcall.
Definition at line 1425 of file TargetLowering.h.
|
inlineinherited |
Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 520 of file TargetLowering.h.
|
inlinevirtualinherited |
Returns the maximal possible offset which can be used for loads / stores from the global.
Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 903 of file TargetLowering.h.
|
inlineinherited |
Get maximum # of store operations permitted for llvm.memcpy.
This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 758 of file TargetLowering.h.
|
inlineinherited |
Get maximum # of store operations permitted for llvm.memmove.
This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 768 of file TargetLowering.h.
|
inlineinherited |
Get maximum # of store operations permitted for llvm.memset.
This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line 748 of file TargetLowering.h.
|
inlineinherited |
Return the minimum function alignment.
Definition at line 873 of file TargetLowering.h.
|
inlineinherited |
Return integer threshold on number of blocks to use jump tables rather than if sequence.
Definition at line 833 of file TargetLowering.h.
|
inlineinherited |
Return the minimum stack alignment of an argument.
Definition at line 868 of file TargetLowering.h.
|
virtualinherited |
Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.
Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.
Definition at line 2442 of file TargetLowering.cpp.
|
inlineinherited |
Return the number of registers that this ValueType will eventually require.
This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.
Definition at line 703 of file TargetLowering.h.
|
inlineinherited |
Definition at line 151 of file TargetLowering.h.
|
inlineinherited |
Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 477 of file TargetLowering.h.
|
overridevirtual |
getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9157 of file PPCISelLowering.cpp.
|
virtualinherited |
Returns relocation base for the given PIC jumptable.
Reimplemented in llvm::X86TargetLowering.
Definition at line 235 of file TargetLowering.cpp.
|
virtualinherited |
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Reimplemented in llvm::X86TargetLowering.
Definition at line 251 of file TargetLowering.cpp.
|
inherited |
Definition at line 847 of file TargetLoweringBase.cpp.
|
virtualinherited |
Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.
Definition at line 843 of file TargetLoweringBase.cpp.
|
inherited |
Definition at line 851 of file TargetLoweringBase.cpp.
|
inlinevirtualinherited |
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.
Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MSP430TargetLowering, and llvm::HexagonTargetLowering.
Definition at line 1881 of file TargetLowering.h.
|
inlinevirtualinherited |
Return the preferred vector type legalization action.
Reimplemented in llvm::X86TargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.
Definition at line 190 of file TargetLowering.h.
|
inlineinherited |
Return the preferred function alignment.
Definition at line 878 of file TargetLowering.h.
|
inlineinherited |
Return the preferred loop alignment.
Definition at line 883 of file TargetLowering.h.
|
overridevirtual |
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.
Reimplemented from llvm::TargetLowering.
Definition at line 1442 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Return the register class that should be used for the specified value type.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 314 of file TargetLowering.h.
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 8889 of file PPCISelLowering.cpp.
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 9118 of file PPCISelLowering.cpp.
Return the type of registers that this ValueType will eventually require.
Definition at line 669 of file TargetLowering.h.
|
inlineinherited |
Return the type of registers that this ValueType will eventually require.
Definition at line 675 of file TargetLowering.h.
|
inlinevirtualinherited |
Return the cost of the 'representative' register class for the specified value type.
Definition at line 334 of file TargetLowering.h.
|
inlinevirtualinherited |
Return the 'representative' register class for the specified value type.
The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.
Reimplemented in llvm::MipsSETargetLowering.
Definition at line 327 of file TargetLowering.h.
|
private |
Definition at line 5109 of file PPCISelLowering.cpp.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 354 of file PPCISelLowering.h.
|
inlinevirtualinherited |
Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 1271 of file TargetLowering.h.
|
inlineinherited |
Return target scheduling preference.
Definition at line 301 of file TargetLowering.h.
|
overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9264 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2344 of file TargetLowering.h.
|
overridevirtual |
getSetCCResultType - Return the ISD::SETCC ValueType
Reimplemented from llvm::TargetLoweringBase.
Definition at line 824 of file PPCISelLowering.cpp.
Definition at line 860 of file TargetLoweringBase.cpp.
|
inlineinherited |
Return the MVT corresponding to this LLVM type. See getValueType.
Definition at line 659 of file TargetLowering.h.
|
overridevirtual |
Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.
Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.
Reimplemented from llvm::TargetLowering.
Definition at line 8837 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.
Reimplemented in llvm::X86TargetLowering.
Definition at line 896 of file TargetLowering.h.
|
inlineinherited |
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 839 of file TargetLowering.h.
|
inlineinherited |
Definition at line 149 of file TargetLowering.h.
|
overridevirtual |
getTargetNodeName() - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 759 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.
Reimplemented in llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 439 of file TargetLowering.h.
|
inlineinherited |
Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line 535 of file TargetLowering.h.
|
inlineinherited |
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.
Definition at line 375 of file TargetLowering.h.
|
inlineinherited |
Definition at line 378 of file TargetLowering.h.
|
inlineinherited |
Reset the operation actions based on target options.
Definition at line 1629 of file TargetLowering.h.
|
inlinevirtualinherited |
Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. FIXME: Most C calling convention requires the return type to be promoted, but this is not true all the time, e.g. i1 on x86-64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2327 of file TargetLowering.h.
Estimate the cost of type-legalization and the legalized type.
Definition at line 1425 of file TargetLoweringBase.cpp.
|
inlineinherited |
For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.
Definition at line 396 of file TargetLowering.h.
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition at line 611 of file TargetLowering.h.
|
inlineinherited |
For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.
Definition at line 388 of file TargetLowering.h.
|
inlineinherited |
Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.
Definition at line 638 of file TargetLowering.h.
|
inlineinherited |
Definition at line 367 of file TargetLowering.h.
|
inlinevirtualinherited |
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 169 of file TargetLowering.h.
|
inherited |
Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
Definition at line 1227 of file TargetLoweringBase.cpp.
|
inlinevirtualinherited |
Target-specific cleanup for formal ByVal parameters.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 2266 of file TargetLowering.h.
|
inlineinherited |
When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.
Definition at line 731 of file TargetLowering.h.
|
inlineinherited |
Return true if the target has BitExtract instructions.
Definition at line 186 of file TargetLowering.h.
|
inlineinherited |
Return true if multiple condition registers are available.
Definition at line 181 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1356 of file TargetLowering.h.
|
inlinevirtualinherited |
Specify maximum number of store instructions per memset call.
When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 1361 of file TargetLowering.h.
|
inlineinherited |
If true, the target has custom DAG combine transformations that it can perform for the specified node.
Definition at line 737 of file TargetLowering.h.
|
protectedinherited |
Initialize all of the actions to default values.
Definition at line 733 of file TargetLoweringBase.cpp.
|
inherited |
Get the ISD node that corresponds to the Instruction class opcode.
Definition at line 1353 of file TargetLoweringBase.cpp.
|
inlineinherited |
Definition at line 153 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified condition code is legal on this target.
Definition at line 602 of file TargetLowering.h.
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
Definition at line 1179 of file TargetLowering.cpp.
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
Definition at line 1149 of file TargetLowering.cpp.
|
inlinevirtualinherited |
Return true if it is profitable to move a following shift through this.
Reimplemented in llvm::AArch64TargetLowering.
Definition at line 2060 of file TargetLowering.h.
|
inlinevirtualinherited |
This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2084 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
Reimplemented in llvm::ARMTargetLowering.
Definition at line 2076 of file TargetLowering.h.
|
private |
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.
Definition at line 3285 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 1382 of file TargetLowering.h.
|
overridevirtual |
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9238 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 1375 of file TargetLowering.h.
|
inlinevirtualinherited |
Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 447 of file TargetLowering.h.
|
virtualinherited |
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2005 of file TargetLowering.cpp.
|
inlineinherited |
Return true if the specified indexed load is legal on this target.
Definition at line 561 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified indexed load is legal on this target.
Definition at line 579 of file TargetLowering.h.
|
inherited |
Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.
Definition at line 48 of file TargetLowering.cpp.
|
inlineinherited |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
Definition at line 215 of file TargetLowering.h.
|
inlineinherited |
Return true if Flow Control is an expensive operation that should be avoided.
Definition at line 231 of file TargetLowering.h.
|
overridevirtual |
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9201 of file PPCISelLowering.cpp.
|
overridevirtual |
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9015 of file PPCISelLowering.cpp.
|
overridevirtual |
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9197 of file PPCISelLowering.cpp.
|
protectedinherited |
Return true if the value types that can be represented by the specified register class are all legal.
isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.
Definition at line 934 of file TargetLoweringBase.cpp.
|
inlineinherited |
Definition at line 154 of file TargetLowering.h.
|
inlinevirtualinherited |
isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Reimplemented in llvm::AMDGPUTargetLowering.
Definition at line 246 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified load with extension is legal on this target.
Definition at line 527 of file TargetLowering.h.
|
inlineinherited |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Definition at line 261 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1402 of file TargetLowering.h.
|
inlinevirtualinherited |
Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 908 of file TargetLowering.h.
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 9141 of file PPCISelLowering.cpp.
|
inlineinherited |
Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.
Definition at line 507 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified operation is legal on this target.
Definition at line 512 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.
Definition at line 489 of file TargetLowering.h.
|
inlineinherited |
Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.
Definition at line 498 of file TargetLowering.h.
|
inlineinherited |
Return true if pow2 div is cheaper than a chain of srl/add/sra.
Definition at line 227 of file TargetLowering.h.
|
inlineinherited |
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
Definition at line 235 of file TargetLowering.h.
|
inlinevirtualinherited |
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented in llvm::X86TargetLowering.
Definition at line 814 of file TargetLowering.h.
|
inlineinherited |
Return true if the select operation is expensive for this target.
Definition at line 174 of file TargetLowering.h.
|
inlinevirtualinherited |
Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 176 of file TargetLowering.h.
|
inlinevirtualinherited |
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::MipsSETargetLowering.
Definition at line 455 of file TargetLowering.h.
|
inlineinherited |
Returns true if target has indicated at least one type should be bypassed.
Definition at line 218 of file TargetLowering.h.
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in register X1 to i32 by referencing its sub-register R1.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9181 of file PPCISelLowering.cpp.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9189 of file PPCISelLowering.cpp.
Return true if the specified store with truncation is legal on this target.
Definition at line 544 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2068 of file TargetLowering.h.
|
inlineinherited |
Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.
Definition at line 341 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call.
This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 2297 of file TargetLowering.h.
|
inlinevirtualinherited |
Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented in llvm::X86TargetLowering.
Definition at line 469 of file TargetLowering.h.
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inlinevirtualinherited |
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.
Reimplemented in llvm::X86TargetLowering.
Definition at line 1295 of file TargetLowering.h.
Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register.
This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1327 of file TargetLowering.h.
Reset the operation actions based on target options.
Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 1331 of file TargetLowering.h.
|
inlinevirtualinherited |
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, llvm::AMDGPUTargetLowering, and llvm::XCoreTargetLowering.
Definition at line 1369 of file TargetLowering.h.
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private |
Definition at line 1962 of file PPCISelLowering.cpp.
|
overridevirtual |
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.
Reimplemented from llvm::TargetLowering.
Definition at line 8945 of file PPCISelLowering.cpp.
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private |
Definition at line 1631 of file PPCISelLowering.cpp.
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private |
Definition at line 5772 of file PPCISelLowering.cpp.
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overrideprivatevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 3872 of file PPCISelLowering.cpp.
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private |
Definition at line 3910 of file PPCISelLowering.cpp.
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private |
Definition at line 4148 of file PPCISelLowering.cpp.
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private |
Definition at line 4623 of file PPCISelLowering.cpp.
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private |
Definition at line 3721 of file PPCISelLowering.cpp.
|
inherited |
This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.
TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.
Definition at line 7072 of file SelectionDAGBuilder.cpp.
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private |
Definition at line 1571 of file PPCISelLowering.cpp.
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inlinevirtualinherited |
|
private |
Definition at line 5158 of file PPCISelLowering.cpp.
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private |
Definition at line 5187 of file PPCISelLowering.cpp.
|
private |
Definition at line 5179 of file PPCISelLowering.cpp.
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private |
Definition at line 5540 of file PPCISelLowering.cpp.
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overrideprivatevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 2301 of file PPCISelLowering.cpp.
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private |
Definition at line 2322 of file PPCISelLowering.cpp.
|
private |
Definition at line 2559 of file PPCISelLowering.cpp.
|
private |
Definition at line 2898 of file PPCISelLowering.cpp.
|
private |
Definition at line 5344 of file PPCISelLowering.cpp.
|
private |
Definition at line 9086 of file PPCISelLowering.cpp.
|
private |
Definition at line 1737 of file PPCISelLowering.cpp.
|
private |
Definition at line 1644 of file PPCISelLowering.cpp.
|
private |
Definition at line 1967 of file PPCISelLowering.cpp.
|
private |
Definition at line 5401 of file PPCISelLowering.cpp.
|
private |
LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom lower, do it, otherwise return null.
Definition at line 6210 of file PPCISelLowering.cpp.
|
private |
Definition at line 1603 of file PPCISelLowering.cpp.
|
private |
Definition at line 5194 of file PPCISelLowering.cpp.
|
private |
Definition at line 6318 of file PPCISelLowering.cpp.
|
overridevirtual |
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 6391 of file PPCISelLowering.cpp.
|
virtualinherited |
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.
TODO: Consider merging with ReplaceNodeResults.
The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.
Reimplemented in llvm::MipsTargetLowering.
Definition at line 7332 of file SelectionDAGBuilder.cpp.
|
overrideprivatevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 5027 of file PPCISelLowering.cpp.
|
private |
Definition at line 9049 of file PPCISelLowering.cpp.
|
private |
Definition at line 6300 of file PPCISelLowering.cpp.
|
private |
LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when possible.
Definition at line 5245 of file PPCISelLowering.cpp.
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private |
Definition at line 1778 of file PPCISelLowering.cpp.
|
private |
Definition at line 5604 of file PPCISelLowering.cpp.
|
private |
Definition at line 6276 of file PPCISelLowering.cpp.
|
private |
Definition at line 5662 of file PPCISelLowering.cpp.
|
private |
Definition at line 5633 of file PPCISelLowering.cpp.
|
private |
Definition at line 5076 of file PPCISelLowering.cpp.
|
private |
Definition at line 5215 of file PPCISelLowering.cpp.
|
private |
Definition at line 5234 of file PPCISelLowering.cpp.
|
private |
Definition at line 1842 of file PPCISelLowering.cpp.
|
private |
Definition at line 1950 of file PPCISelLowering.cpp.
|
private |
Definition at line 2006 of file PPCISelLowering.cpp.
|
private |
LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this is a shuffle we can handle in a single instruction, return it. Otherwise, return the code it can be lowered into. Worst case, it can always be lowered into a vperm.
Definition at line 6027 of file PPCISelLowering.cpp.
Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.
LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.
Reimplemented in llvm::X86TargetLowering.
Definition at line 2091 of file TargetLowering.cpp.
|
inherited |
Returns a pair of (return value, chain).
Generate a libcall taking the given operands as arguments and returning a result of type RetVT.
Definition at line 86 of file TargetLowering.cpp.
|
inlinevirtualinherited |
Return true if the target may be able emit the call instruction as a tail call. This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.
Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SystemZTargetLowering.
Definition at line 2304 of file TargetLowering.h.
|
virtualinherited |
Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.
ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.
ConstraintOperands - Information about all of the constraints.
Definition at line 2233 of file TargetLowering.cpp.
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overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 8176 of file PPCISelLowering.cpp.
|
inlinevirtualinherited |
This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.
Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.
Reimplemented in llvm::SystemZTargetLowering.
Definition at line 2355 of file TargetLowering.h.
|
overridevirtual |
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.
Reimplemented from llvm::TargetLowering.
Definition at line 6451 of file PPCISelLowering.cpp.
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inlinevirtualinherited |
Reset the operation actions based on target options.
Reimplemented in llvm::X86TargetLowering.
Definition at line 959 of file TargetLowering.h.
| bool PPCTargetLowering::SelectAddressRegImm | ( | SDValue | N, |
| SDValue & | Disp, | ||
| SDValue & | Base, | ||
| SelectionDAG & | DAG, | ||
| bool | Aligned | ||
| ) | const |
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg. If Aligned is true, only accept displacements suitable for STD and friends, i.e. multiples of 4.
Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg. If Aligned is true, only accept displacements suitable for STD and friends, i.e. multiples of 4.
Definition at line 1316 of file PPCISelLowering.cpp.
| bool PPCTargetLowering::SelectAddressRegReg | ( | SDValue | N, |
| SDValue & | Base, | ||
| SDValue & | Index, | ||
| SelectionDAG & | DAG | ||
| ) | const |
SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an indexed [r+r] operation. Returns false if it can be more efficiently represented with [r+imm].
Definition at line 1231 of file PPCISelLowering.cpp.
| bool PPCTargetLowering::SelectAddressRegRegOnly | ( | SDValue | N, |
| SDValue & | Base, | ||
| SDValue & | Index, | ||
| SelectionDAG & | DAG | ||
| ) | const |
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+r] operation.
Definition at line 1414 of file PPCISelLowering.cpp.
|
inlineprotectedinherited |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.
Definition at line 964 of file TargetLowering.h.
|
inlineprotectedinherited |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.
Definition at line 971 of file TargetLowering.h.
|
inlineprotectedinherited |
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.
Definition at line 978 of file TargetLowering.h.
|
inlineinherited |
Override the default CondCode to be used to test the result of the comparison libcall against zero.
Definition at line 1431 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.
The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.
Definition at line 1156 of file TargetLowering.h.
|
inlineprotectedinherited |
If set to a physical register, this sets the register that receives the exception address on entry to a landing pad.
Definition at line 1018 of file TargetLowering.h.
|
inlineprotectedinherited |
If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad.
Definition at line 1024 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.
Definition at line 1047 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.
Definition at line 1039 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.
NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp
Definition at line 1131 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp
Definition at line 1145 of file TargetLowering.h.
|
inlineprotectedinherited |
Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic.
Definition at line 1222 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.
Definition at line 1060 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the target's required jmp_buf buffer alignment (in bytes); default is 0
Definition at line 1192 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the target's required jmp_buf buffer size (in bytes); default is 200.
Definition at line 1186 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator not to expand sequence of operations into a separate sequences that increases the amount of flow control.
Definition at line 1053 of file TargetLowering.h.
|
inlineinherited |
Set the CallingConv that should be used for the specified libcall.
Definition at line 1442 of file TargetLowering.h.
|
inlineinherited |
Rename the default libcall routine name for the specified libcall.
Definition at line 1420 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.
Definition at line 1110 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the target's minimum function alignment (in log2(bytes))
Definition at line 1197 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate the number of blocks to generate jump tables rather than if sequence.
Definition at line 1006 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the minimum stack alignment of an argument (in log2(bytes)).
Definition at line 1216 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified operation does not work with the specified type and indicate what to do about it.
Definition at line 1102 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.
Definition at line 1069 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))
Definition at line 1204 of file TargetLowering.h.
|
inlineprotectedinherited |
Set the target's preferred loop alignment. Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes).
Definition at line 1211 of file TargetLowering.h.
|
inlineprotectedinherited |
Specify the target scheduling preference.
Definition at line 983 of file TargetLowering.h.
|
inlineprotectedinherited |
Tells the code generator not to expand operations into sequences that use the select operations if possible.
Definition at line 1030 of file TargetLowering.h.
|
inlineprotectedinherited |
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line 1012 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate whether the target can generate code for jump tables.
Definition at line 1000 of file TargetLowering.h.
|
inlineprotectedinherited |
Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.
Definition at line 1180 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.
Definition at line 1119 of file TargetLowering.h.
|
inlineprotectedinherited |
Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. Defaults to false.
Definition at line 995 of file TargetLowering.h.
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inlineprotectedinherited |
Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. Defaults to false.
Definition at line 989 of file TargetLowering.h.
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overridevirtual |
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9171 of file PPCISelLowering.cpp.
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inlinevirtualinherited |
Return true if the given (atomic) instruction should be expanded by the IR-level AtomicExpandLoadLinked pass into a loop involving load-linked/store-conditional pairs. Atomic stores will be expanded in the same way as "atomic xchg" operations which ignore their output if needed.
Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.
Definition at line 948 of file TargetLowering.h.
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9256 of file PPCISelLowering.cpp.
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inlinevirtualinherited |
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.
Definition at line 726 of file TargetLowering.h.
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inherited |
Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.
SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.
Definition at line 372 of file TargetLowering.cpp.
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inherited |
Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.
SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.
Definition at line 1206 of file TargetLowering.cpp.
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inherited |
SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.
Definition at line 117 of file TargetLowering.cpp.
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inlineinherited |
Return whether the target can generate code for jump tables.
Definition at line 827 of file TargetLowering.h.
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private |
Definition at line 2107 of file PPCISelLowering.cpp.
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inlineinherited |
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
Definition at line 822 of file TargetLowering.h.
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inlineinherited |
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
Definition at line 817 of file TargetLowering.h.
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inherited |
Definition at line 2772 of file TargetLowering.cpp.
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protectedinherited |
MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.
Definition at line 1842 of file TargetLowering.h.
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protectedinherited |
Specify maximum bytes of store instructions per memcpy call.
When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.
Definition at line 1814 of file TargetLowering.h.
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protectedinherited |
Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute.
Definition at line 1818 of file TargetLowering.h.
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protectedinherited |
Specify maximum bytes of store instructions per memmove call.
When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.
Definition at line 1830 of file TargetLowering.h.
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protectedinherited |
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.
Definition at line 1834 of file TargetLowering.h.
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protectedinherited |
Specify maximum number of store instructions per memset call.
When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
Definition at line 1797 of file TargetLowering.h.
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protectedinherited |
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
Definition at line 1801 of file TargetLowering.h.
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protectedinherited |
Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.
Definition at line 1838 of file TargetLowering.h.
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private |
Definition at line 345 of file PPCISelLowering.h.
1.8.6 
