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llvm::PPCTargetLowering Class Reference

#include <PPCISelLowering.h>

+ Inheritance diagram for llvm::PPCTargetLowering:

Public Types

enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntryArgListTy
 
typedef std::vector
< AsmOperandInfo
AsmOperandInfoVector
 
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector
}
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
typedef std::pair
< LegalizeTypeAction, EVT
LegalizeKind
 

Public Member Functions

 PPCTargetLowering (PPCTargetMachine &TM)
 
const char * getTargetNodeName (unsigned Opcode) const override
 
MVT getScalarShiftAmountTy (EVT LHSTy) const override
 
EVT getSetCCResultType (LLVMContext &Context, EVT VT) const override
 getSetCCResultType - Return the ISD::SETCC ValueType More...
 
bool getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
 
bool SelectAddressRegReg (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
 
bool SelectAddressRegImm (SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const
 
bool SelectAddressRegRegOnly (SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
 
Sched::Preference getSchedulingPreference (SDNode *N) const override
 
SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const override
 
void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
 
SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
 
unsigned getRegisterByName (const char *RegName, EVT VT) const override
 
void computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
 
MachineBasicBlockEmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override
 
MachineBasicBlockEmitAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is64Bit, unsigned BinOpcode) const
 
MachineBasicBlockEmitPartwordAtomicBinary (MachineInstr *MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode) const
 
MachineBasicBlockemitEHSjLjSetJmp (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlockemitEHSjLjLongJmp (MachineInstr *MI, MachineBasicBlock *MBB) const
 
ConstraintType getConstraintType (const std::string &Constraint) const override
 
ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
 
std::pair< unsigned, const
TargetRegisterClass * > 
getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const override
 
unsigned getByValTypeAlignment (Type *Ty) const override
 
void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
 
bool isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override
 
bool isLegalICmpImmediate (int64_t Imm) const override
 
bool isLegalAddImmediate (int64_t Imm) const override
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const override
 
bool isTruncateFree (EVT VT1, EVT VT2) const override
 
bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
 Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override
 
EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
 
bool allowsUnalignedMemoryAccesses (EVT VT, unsigned AddrSpace, bool *Fast=nullptr) const override
 
bool isFMAFasterThanFMulAndFAdd (EVT VT) const override
 
bool shouldExpandBuildVectorWithShuffles (EVT VT, unsigned DefinedValues) const override
 
FastISelcreateFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
 
bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
 Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv. More...
 
virtual bool getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 
virtual unsigned getJumpTableEncoding () const
 
virtual const MCExprLowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 Returns relocation base for the given PIC jumptable. More...
 
virtual const MCExprgetPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 
std::pair< SDValue, SDValuemakeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
 
bool isConstTrueVal (const SDNode *N) const
 
bool isConstFalseVal (const SDNode *N) const
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 
virtual bool isDesirableToCommuteWithShift (const SDNode *N) const
 Return true if it is profitable to move a following shift through this. More...
 
virtual bool isTypeDesirableForOp (unsigned, EVT VT) const
 
virtual bool isDesirableToTransformToIntegerOp (unsigned, EVT) const
 
virtual bool IsDesirableToPromoteOp (SDValue, EVT &) const
 
std::pair< SDValue, SDValueLowerCallTo (CallLoweringInfo &CLI) const
 
virtual void HandleByVal (CCState *, unsigned &, unsigned) const
 Target-specific cleanup for formal ByVal parameters. More...
 
virtual bool isUsedByReturnOnly (SDNode *, SDValue &) const
 
virtual bool mayBeEmittedAsTailCall (CallInst *) const
 
virtual const char * getClearCacheBuiltinName () const
 
virtual MVT getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const
 
virtual const MCPhysReggetScratchRegisters (CallingConv::ID CC) const
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual bool ExpandInlineAsm (CallInst *) const
 
virtual AsmOperandInfoVector ParseConstraints (ImmutableCallSite CS) const
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 
virtual const char * LowerXConstraint (EVT ConstraintVT) const
 
SDValue BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
 Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 
virtual void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const
 
const TargetMachinegetTargetMachine () const
 
const DataLayoutgetDataLayout () const
 
const TargetLoweringObjectFilegetObjFileLowering () const
 
bool isBigEndian () const
 
bool isLittleEndian () const
 
virtual MVT getPointerTy (uint32_t=0) const
 
unsigned getPointerSizeInBits (uint32_t AS=0) const
 
unsigned getPointerTypeSizeInBits (Type *Ty) const
 
EVT getShiftAmountTy (EVT LHSTy) const
 
virtual MVT getVectorIdxTy () const
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual
TargetLoweringBase::LegalizeTypeAction 
getPreferredVectorAction (EVT VT) const
 Return the preferred vector type legalization action. More...
 
bool isIntDivCheap () const
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 
getBypassSlowDivWidths () const
 
bool isPow2DivCheap () const
 Return true if pow2 div is cheaper than a chain of srl/add/sra. More...
 
bool isJumpExpensive () const
 
bool isPredictableSelectExpensive () const
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual const TargetRegisterClassgetRegClassFor (MVT VT) const
 
virtual const TargetRegisterClassgetRepRegClassFor (MVT VT) const
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 
bool isTypeLegal (EVT VT) const
 
const ValueTypeActionImplgetValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 
virtual bool isFPImmLegal (const APFloat &, EVT) const
 
virtual bool isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 
bool isOperationExpand (unsigned Op, EVT VT) const
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, MVT VT) const
 
bool isLoadExtLegal (unsigned ExtType, EVT VT) const
 Return true if the specified load with extension is legal on this target. More...
 
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 
EVT getValueType (Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 
virtual bool ShouldShrinkFPConstant (EVT) const
 
bool hasBigEndianPartOrdering (EVT VT) const
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
virtual bool isSafeMemOpType (MVT) const
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
bool supportJumpTables () const
 Return whether the target can generate code for jump tables. More...
 
int getMinimumJumpTableEntries () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 
unsigned getExceptionPointerRegister () const
 
unsigned getExceptionSelectorRegister () const
 
unsigned getJumpBufSize () const
 
unsigned getJumpBufAlignment () const
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
unsigned getPrefLoopAlignment () const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 
virtual bool getStackCookieLocation (unsigned &, unsigned &) const
 
virtual unsigned getMaximalGlobalOffset () const
 
virtual bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVTgetTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

void initActions ()
 Initialize all of the actions to default values. More...
 

Private Member Functions

SDValue getFramePointerFrameIndex (SelectionDAG &DAG) const
 
SDValue getReturnAddrFrameIndex (SelectionDAG &DAG) const
 
bool IsEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
 
SDValue EmitTailCallLoadFPAndRetAddr (SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, SDLoc dl) const
 
SDValue LowerRETURNADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFRAMEADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerConstantPool (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBlockAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerJumpTable (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSETCC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINIT_TRAMPOLINE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerADJUST_TRAMPOLINE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
 
SDValue LowerVAARG (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
 
SDValue LowerVACOPY (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
 
SDValue LowerSTACKRESTORE (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
 
SDValue LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
 
SDValue LowerLOAD (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSTORE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerTRUNCATE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT_CC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_TO_INT (SDValue Op, SelectionDAG &DAG, SDLoc dl) const
 
SDValue LowerINT_TO_FP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFLT_ROUNDS_ (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSHL_PARTS (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSRL_PARTS (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSRA_PARTS (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINTRINSIC_WO_CHAIN (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSCALAR_TO_VECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSIGN_EXTEND_INREG (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerMUL (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue FinishCall (CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
 
SDValue LowerCall (TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
 
bool CanLowerReturn (CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
 
SDValue LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
 
SDValue extendArgForPPC64 (ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, SDLoc dl) const
 
SDValue LowerFormalArguments_Darwin (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerFormalArguments_64SVR4 (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerFormalArguments_32SVR4 (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue createMemcpyOutsideCallSeq (SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) const
 
SDValue LowerCall_Darwin (SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerCall_64SVR4 (SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerCall_32SVR4 (SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue lowerEH_SJLJ_SETJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue lowerEH_SJLJ_LONGJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue DAGCombineExtBoolTrunc (SDNode *N, DAGCombinerInfo &DCI) const
 
SDValue DAGCombineTruncBoolExt (SDNode *N, DAGCombinerInfo &DCI) const
 
SDValue DAGCombineFastRecip (SDValue Op, DAGCombinerInfo &DCI) const
 
SDValue DAGCombineFastRecipFSQRT (SDValue Op, DAGCombinerInfo &DCI) const
 
CCAssignFnuseFastISelCCs (unsigned Flag) const
 

Private Attributes

const PPCSubtargetSubtarget
 

Helpers for load-linked/store-conditional atomic expansion.

virtual ValueemitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
 
virtual ValueemitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 
virtual bool shouldExpandAtomicInIR (Instruction *Inst) const
 
virtual void resetOperationActions ()
 Reset the operation actions based on target options. More...
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 
virtual int getScalingFactorCost (const AddrMode &AM, Type *Ty) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool isVectorShiftByScalarCheap (Type *Ty) const
 
virtual bool allowTruncateForTailCall (Type *, Type *) const
 
virtual bool isZExtFree (Type *, Type *) const
 
virtual bool isZExtFree (EVT, EVT) const
 Reset the operation actions based on target options. More...
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 Specify maximum number of store instructions per memset call. More...
 
virtual bool isFNegFree (EVT VT) const
 
virtual bool isFAbsFree (EVT VT) const
 
virtual bool isNarrowingProfitable (EVT, EVT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 Reset the operation actions based on target options. More...
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 
bool PredictableSelectIsExpensive
 
bool MaskAndBranchFoldingIsLegal
 
void setBooleanContents (BooleanContent Ty)
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 
void setBooleanVectorContents (BooleanContent Ty)
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 
void setUseUnderscoreLongJmp (bool Val)
 
void setSupportJumpTables (bool Val)
 Indicate whether the target can generate code for jump tables. More...
 
void setMinimumJumpTableEntries (int Val)
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 
void setExceptionPointerRegister (unsigned R)
 
void setExceptionSelectorRegister (unsigned R)
 
void setSelectIsExpensive (bool isExpensive=true)
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 
void setJumpIsExpensive (bool isExpensive=true)
 
void setIntDivIsCheap (bool isCheap=true)
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2DivIsCheap (bool isCheap=true)
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
virtual std::pair< const
TargetRegisterClass *, uint8_t > 
findRepresentativeClass (MVT VT) const
 
void computeRegisterProperties ()
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ISD::NodeType NT)
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 
void setPrefLoopAlignment (unsigned Align)
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 
bool isLegalRC (const TargetRegisterClass *RC) const
 
MachineBasicBlockemitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 

Detailed Description

Definition at line 344 of file PPCISelLowering.h.

Member Typedef Documentation

typedef std::vector<ArgListEntry> llvm::TargetLowering::ArgListTy
inherited

Definition at line 2126 of file TargetLowering.h.

Definition at line 2484 of file TargetLowering.h.

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 106 of file TargetLowering.h.

Member Enumeration Documentation

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 109 of file TargetLowering.h.

Enumerator
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 2425 of file TargetLowering.h.

2425  {
2426  C_Register, // Constraint represents specific register(s).
2427  C_RegisterClass, // Constraint represents any of register(s) in class.
2428  C_Memory, // Memory constraint.
2429  C_Other, // Something else.
2430  C_Unknown // Unsupported constraint.
2431  };
Enumerator
CW_Invalid 
CW_Okay 
CW_Good 
CW_Better 
CW_Best 
CW_SpecificReg 
CW_Register 
CW_Memory 
CW_Constant 
CW_Default 

Definition at line 2433 of file TargetLowering.h.

2433  {
2434  // Generic weights.
2435  CW_Invalid = -1, // No match.
2436  CW_Okay = 0, // Acceptable.
2437  CW_Good = 1, // Good weight.
2438  CW_Better = 2, // Better weight.
2439  CW_Best = 3, // Best weight.
2440 
2441  // Well-known weights.
2442  CW_SpecificReg = CW_Okay, // Specific register operands.
2443  CW_Register = CW_Good, // Register operands.
2444  CW_Memory = CW_Better, // Memory operands.
2445  CW_Constant = CW_Best, // Constant operand.
2446  CW_Default = CW_Okay // Default or don't know type.
2447  };

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
Custom 

Definition at line 84 of file TargetLowering.h.

84  {
85  Legal, // The target natively supports this operation.
86  Promote, // This operation should be executed in a larger type.
87  Expand, // Try to expand this to other ops, otherwise use a libcall.
88  Custom // Use the LowerOperation hook to implement custom lowering.
89  };

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 

Definition at line 93 of file TargetLowering.h.

93  {
94  TypeLegal, // The target natively supports this type.
95  TypePromoteInteger, // Replace this integer with a larger one.
96  TypeExpandInteger, // Split this integer into two of half the size.
97  TypeSoftenFloat, // Convert this float to a same size integer type.
98  TypeExpandFloat, // Split this float into two of half the size.
99  TypeScalarizeVector, // Replace this one-element vector with its element.
100  TypeSplitVector, // Split this vector into two of half the size.
101  TypeWidenVector // This vector should be widened into a larger vector.
102  };

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 116 of file TargetLowering.h.

116  {
117  ScalarValSelect, // The target supports scalar selects (ex: cmov).
118  ScalarCondVectorVal, // The target supports selects with a scalar condition
119  // and vector values (ex: cmov).
120  VectorMaskSelect // The target supports vector selects with a vector
121  // mask (ex: x86 blends).
122  };

Constructor & Destructor Documentation

PPCTargetLowering::PPCTargetLowering ( PPCTargetMachine TM)
explicit

Definition at line 63 of file PPCISelLowering.cpp.

67 
68  // Use _setjmp/_longjmp instead of setjmp/longjmp.
71 
72  // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73  // arguments are at least 4/8 bytes aligned.
74  bool isPPC64 = Subtarget.isPPC64();
75  setMinStackArgumentAlignment(isPPC64 ? 8:4);
76 
77  // Set up the register classes.
78  addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79  addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80  addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
81 
82  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
85 
87 
88  // PowerPC has pre-inc load and store's.
99 
100  if (Subtarget.useCRBits()) {
102 
103  if (isPPC64 || Subtarget.hasFPCVT()) {
106  isPPC64 ? MVT::i64 : MVT::i32);
109  isPPC64 ? MVT::i64 : MVT::i32);
110  } else {
113  }
114 
115  // PowerPC does not support direct load / store of condition registers
118 
119  // FIXME: Remove this once the ANDI glue bug is fixed:
120  if (ANDIGlueBug)
122 
129 
130  addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
131  }
132 
133  // This is used in the ppcf128->int sequence. Note it has different semantics
134  // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 
137  // We do not currently implement these libm ops for PowerPC.
144 
145  // PowerPC has no SREM/UREM instructions
150 
151  // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
160 
161  // We don't support sin/cos/sqrt/fmod/pow
174 
176 
177  // If we're enabling GP optimizations, use hardware square root
178  if (!Subtarget.hasFSQRT() &&
179  !(TM.Options.UnsafeFPMath &&
182 
183  if (!Subtarget.hasFSQRT() &&
184  !(TM.Options.UnsafeFPMath &&
187 
188  if (Subtarget.hasFCPSGN()) {
191  } else {
194  }
195 
196  if (Subtarget.hasFPRND()) {
201 
206  }
207 
208  // PowerPC does not have BSWAP, CTPOP or CTTZ
217 
218  if (Subtarget.hasPOPCNTD()) {
221  } else {
224  }
225 
226  // PowerPC does not have ROTR
229 
230  if (!Subtarget.useCRBits()) {
231  // PowerPC does not have Select
236  }
237 
238  // PowerPC wants to turn select_cc of FP into fsel when possible.
241 
242  // PowerPC wants to optimize integer setcc a bit
243  if (!Subtarget.useCRBits())
245 
246  // PowerPC does not have BRCOND which requires SetCC
247  if (!Subtarget.useCRBits())
249 
251 
252  // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 
255  // PowerPC does not have [U|S]INT_TO_FP
258 
263 
264  // We cannot sextinreg(i1). Expand to shifts.
266 
267  // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268  // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269  // support continuation, user-level threading, and etc.. As a result, no
270  // other SjLj exception interfaces are implemented and please don't build
271  // your own exception handling based on them.
272  // LLVM/Clang supports zero-cost DWARF exception handling.
275 
276  // We want to legalize GlobalAddress and ConstantPool nodes into the
277  // appropriate instructions to materialize the address.
288 
289  // TRAP is legal.
291 
292  // TRAMPOLINE is custom lowered.
295 
296  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 
299  if (Subtarget.isSVR4ABI()) {
300  if (isPPC64) {
301  // VAARG always uses double-word chunks, so promote anything smaller.
311  } else {
312  // VAARG is custom lowered with the 32-bit SVR4 ABI.
315  }
316  } else
318 
319  if (Subtarget.isSVR4ABI() && !isPPC64)
320  // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322  else
324 
325  // Use the default implementation.
331 
332  // We want to custom lower some of our intrinsics.
334 
335  // To handle counter-based loop conditions.
337 
338  // Comparisons that require checking two conditions.
351 
352  if (Subtarget.has64BitSupport()) {
353  // They also have instructions for converting between i64 and fp.
358  // This is just the low 32 bits of a (signed) fp->i64 conversion.
359  // We cannot do this with Promote because i64 is not a legal type.
361 
364  } else {
365  // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367  }
368 
369  // With the instructions enabled under FPCVT, we can do everything.
370  if (Subtarget.hasFPCVT()) {
371  if (Subtarget.has64BitSupport()) {
376  }
377 
382  }
383 
384  if (Subtarget.use64BitRegs()) {
385  // 64-bit PowerPC implementations can support i64 types directly
386  addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387  // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389  // 64-bit PowerPC wants to expand i128 shifts itself.
393  } else {
394  // 32-bit PowerPC wants to expand i64 shifts itself.
398  }
399 
400  if (Subtarget.hasAltivec()) {
401  // First set operation action for all vector types to expand. Then we
402  // will selectively turn on ones that can be effectively codegen'd.
403  for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
406 
407  // add/sub are legal for all supported vector VT's.
410 
411  // We promote all shuffles to v16i8.
414 
415  // We promote all non-typed operations to v4i32.
428 
429  // No other operations are legal.
472 
473  for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
474  j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
476  setTruncStoreAction(VT, InnerVT, Expand);
477  }
481  }
482 
483  // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
484  // with merges, splats, etc.
486 
502 
503  addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
504  addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
505  addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
506  addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
507 
510 
511  if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
514  }
515 
519 
522 
527 
528  // Altivec does not contain unordered floating-point compare instructions
533 
534  if (Subtarget.hasVSX()) {
537 
543 
545 
548 
551 
557 
558  // Share the Altivec comparison restrictions.
563 
566 
568 
569  addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
570 
571  addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
572  addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
573 
574  // VSX v2i64 only supports non-arithmetic operations.
577 
581 
583 
588 
590 
595 
596  // Vector operation legalization checks the result type of
597  // SIGN_EXTEND_INREG, overall legalization checks the inner type.
602 
603  addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
604  }
605  }
606 
607  if (Subtarget.has64BitSupport()) {
610  }
611 
616 
618  // Altivec instructions set fields to all zeros or all ones.
620 
621  if (!isPPC64) {
622  // These libcalls are not available in 32-bit.
626  }
627 
628  if (isPPC64) {
632  } else {
636  }
637 
638  // We have target-specific dag combine patterns for the following nodes:
643  if (Subtarget.useCRBits())
647 
651 
652  if (Subtarget.useCRBits()) {
656  }
657 
658  // Use reciprocal estimates.
659  if (TM.Options.UnsafeFPMath) {
662  }
663 
664  // Darwin long double math library functions have $LDBL128 appended.
665  if (Subtarget.isDarwin()) {
666  setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667  setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668  setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669  setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670  setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671  setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672  setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673  setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674  setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675  setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
676  }
677 
678  // With 32 condition bits, we don't need to sink (and duplicate) compares
679  // aggressively in CodeGenPrep.
680  if (Subtarget.useCRBits())
682 
684  if (Subtarget.isDarwin())
686 
687  if (isPPC64 && Subtarget.isJITCodeModel())
688  // Temporary workaround for the inability of PPC64 JIT to handle jump
689  // tables.
690  setSupportJumpTables(false);
691 
693 
696  else
698 
700 
701  // The Freescale cores does better with aggressive inlining of memcpy and
702  // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
705  MaxStoresPerMemset = 32;
707  MaxStoresPerMemcpy = 32;
709  MaxStoresPerMemmove = 32;
711 
713  }
714 }
cl::opt< bool > ANDIGlueBug
bool use64BitRegs() const
Definition: PPCSubtarget.h:177
#define R4(n)
bool hasPOPCNTD() const
Definition: PPCSubtarget.h:212
void setSupportJumpTables(bool Val)
Indicate whether the target can generate code for jump tables.
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:221
void setBooleanVectorContents(BooleanContent Ty)
bool hasAltivec() const
Definition: PPCSubtarget.h:207
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
bool hasFPRND() const
Definition: PPCSubtarget.h:205
bool isJITCodeModel() const
Definition: PPCSubtarget.h:190
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
const PPCSubtarget & Subtarget
static TargetLoweringObjectFile * createTLOF(const Triple &TT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
void setTargetDAGCombine(ISD::NodeType NT)
void setBooleanContents(BooleanContent Ty)
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
void setPrefFunctionAlignment(unsigned Align)
bool hasFSQRT() const
Definition: PPCSubtarget.h:197
bool has64BitSupport() const
Definition: PPCSubtarget.h:172
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:317
bool hasFPCVT() const
Definition: PPCSubtarget.h:206
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
void setUseUnderscoreLongJmp(bool Val)
bool hasLFIWAX() const
Definition: PPCSubtarget.h:204
void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)
TargetLowering(const TargetLowering &) LLVM_DELETED_FUNCTION
void setExceptionPointerRegister(unsigned R)
const PPCSubtarget * getSubtargetImpl() const override
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:314
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
bool isPPC64() const
Definition: PPCSubtarget.h:168
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
void setExceptionSelectorRegister(unsigned R)
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
const StringRef getTargetTriple() const
bool enableMachineScheduler() const override
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
bool hasVSX() const
Definition: PPCSubtarget.h:209
void setStackPointerRegisterToSaveRestore(unsigned R)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool useCRBits() const
Definition: PPCSubtarget.h:181
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
void setUseUnderscoreSetJmp(bool Val)
void setInsertFencesForAtomic(bool fence)
unsigned getDarwinDirective() const
Definition: PPCSubtarget.h:142
bool hasFRSQRTE() const
Definition: PPCSubtarget.h:200
bool hasFRES() const
Definition: PPCSubtarget.h:199
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
bool hasFCPSGN() const
Definition: PPCSubtarget.h:196
bool hasFRE() const
Definition: PPCSubtarget.h:198
void setPow2DivIsCheap(bool isCheap=true)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool hasFRSQRTES() const
Definition: PPCSubtarget.h:201
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Member Function Documentation

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotectedinherited

Tells the code generator which bitwidths to bypass.

Definition at line 1063 of file TargetLowering.h.

1063  {
1064  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1065  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotectedinherited

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1173 of file TargetLowering.h.

1173  {
1174  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1175  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass RC 
)
inlineprotectedinherited

Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Definition at line 1074 of file TargetLowering.h.

1074  {
1075  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1076  AvailableRegClasses.push_back(std::make_pair(VT, RC));
1077  RegClassForVT[VT.SimpleTy] = RC;
1078  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void TargetLowering::AdjustInstrPostInstrSelection ( MachineInstr MI,
SDNode Node 
) const
virtualinherited

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 325 of file SelectionDAGISel.cpp.

326  {
327  assert(!MI->hasPostISelHook() &&
328  "If a target marks an instruction with 'hasPostISelHook', "
329  "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
330 }
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:595
assert(Globals.size() > 1)
bool PPCTargetLowering::allowsUnalignedMemoryAccesses ( EVT  VT,
unsigned  AddrSpace,
bool *  Fast = nullptr 
) const
overridevirtual

Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9205 of file PPCISelLowering.cpp.

9207  {
9208  if (DisablePPCUnaligned)
9209  return false;
9210 
9211  // PowerPC supports unaligned memory access for simple non-vector types.
9212  // Although accessing unaligned addresses is not as efficient as accessing
9213  // aligned addresses, it is generally more efficient than manual expansion,
9214  // and generally only traps for software emulation when crossing page
9215  // boundaries.
9216 
9217  if (!VT.isSimple())
9218  return false;
9219 
9220  if (VT.getSimpleVT().isVector()) {
9221  if (Subtarget.hasVSX()) {
9222  if (VT != MVT::v2f64 && VT != MVT::v2i64)
9223  return false;
9224  } else {
9225  return false;
9226  }
9227  }
9228 
9229  if (VT == MVT::ppcf128)
9230  return false;
9231 
9232  if (Fast)
9233  *Fast = true;
9234 
9235  return true;
9236 }
static cl::opt< bool > DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
const PPCSubtarget & Subtarget
bool isVector() const
isVector - Return true if this is a vector value type.
bool hasVSX() const
Definition: PPCSubtarget.h:209
bool isSimple() const
Definition: ValueTypes.h:95
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLoweringBase::allowTruncateForTailCall ( Type ,
Type  
) const
inlinevirtualinherited

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1311 of file TargetLowering.h.

1311  {
1312  return false;
1313  }
SDValue TargetLowering::BuildExactSDIV ( SDValue  Op1,
SDValue  Op2,
SDLoc  dl,
SelectionDAG DAG 
) const
inherited

Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.

Definition at line 2617 of file TargetLowering.cpp.

2618  {
2619  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2620  APInt d = C->getAPIntValue();
2621  assert(d != 0 && "Division by zero!");
2622 
2623  // Shift the value upfront if it is even, so the LSB is one.
2624  unsigned ShAmt = d.countTrailingZeros();
2625  if (ShAmt) {
2626  // TODO: For UDIV use SRL instead of SRA.
2627  SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2628  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2629  true);
2630  d = d.ashr(ShAmt);
2631  }
2632 
2633  // Calculate the multiplicative inverse, using Newton's method.
2634  APInt t, xn = d;
2635  while ((t = d*xn) != 1)
2636  xn *= APInt(d.getBitWidth(), 2) - t;
2637 
2638  Op2 = DAG.getConstant(xn, Op1.getValueType());
2639  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2640 }
EVT getShiftAmountTy(EVT LHSTy) const
const APInt & getAPIntValue() const
int d()
assert(Globals.size() > 1)
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildSDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2646 of file TargetLowering.cpp.

2648  {
2649  EVT VT = N->getValueType(0);
2650  SDLoc dl(N);
2651 
2652  // Check to see if we can do this.
2653  // FIXME: We should be more aggressive here.
2654  if (!isTypeLegal(VT))
2655  return SDValue();
2656 
2657  APInt::ms magics = Divisor.magic();
2658 
2659  // Multiply the numerator (operand 0) by the magic value
2660  // FIXME: We should support doing a MUL in a wider type
2661  SDValue Q;
2662  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2664  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2665  DAG.getConstant(magics.m, VT));
2666  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2668  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2669  N->getOperand(0),
2670  DAG.getConstant(magics.m, VT)).getNode(), 1);
2671  else
2672  return SDValue(); // No mulhs or equvialent
2673  // If d > 0 and m < 0, add the numerator
2674  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2675  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2676  if (Created)
2677  Created->push_back(Q.getNode());
2678  }
2679  // If d < 0 and m > 0, subtract the numerator.
2680  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2681  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2682  if (Created)
2683  Created->push_back(Q.getNode());
2684  }
2685  // Shift right algebraic if shift value is nonzero
2686  if (magics.s > 0) {
2687  Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2688  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2689  if (Created)
2690  Created->push_back(Q.getNode());
2691  }
2692  // Extract the sign bit and add it to the quotient
2693  SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2694  DAG.getConstant(VT.getScalarSizeInBits() - 1,
2696  if (Created)
2697  Created->push_back(T.getNode());
2698  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2699 }
unsigned s
shift amount
Definition: APInt.h:1699
const SDValue & getOperand(unsigned Num) const
ms magic() const
Definition: APInt.cpp:1396
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:320
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
#define T
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
bool isTypeLegal(EVT VT) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:333
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Magic data for optimising signed division by a constant.
Definition: APInt.h:1697
APInt m
magic number
Definition: APInt.h:1698
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue TargetLowering::BuildUDIV ( SDNode N,
const APInt Divisor,
SelectionDAG DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2705 of file TargetLowering.cpp.

2707  {
2708  EVT VT = N->getValueType(0);
2709  SDLoc dl(N);
2710 
2711  // Check to see if we can do this.
2712  // FIXME: We should be more aggressive here.
2713  if (!isTypeLegal(VT))
2714  return SDValue();
2715 
2716  // FIXME: We should use a narrower constant when the upper
2717  // bits are known to be zero.
2718  APInt::mu magics = Divisor.magicu();
2719 
2720  SDValue Q = N->getOperand(0);
2721 
2722  // If the divisor is even, we can avoid using the expensive fixup by shifting
2723  // the divided value upfront.
2724  if (magics.a != 0 && !Divisor[0]) {
2725  unsigned Shift = Divisor.countTrailingZeros();
2726  Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2727  DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2728  if (Created)
2729  Created->push_back(Q.getNode());
2730 
2731  // Get magic number for the shifted divisor.
2732  magics = Divisor.lshr(Shift).magicu(Shift);
2733  assert(magics.a == 0 && "Should use cheap fixup now");
2734  }
2735 
2736  // Multiply the numerator (operand 0) by the magic value
2737  // FIXME: We should support doing a MUL in a wider type
2738  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2740  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2741  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2743  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2744  DAG.getConstant(magics.m, VT)).getNode(), 1);
2745  else
2746  return SDValue(); // No mulhu or equvialent
2747  if (Created)
2748  Created->push_back(Q.getNode());
2749 
2750  if (magics.a == 0) {
2751  assert(magics.s < Divisor.getBitWidth() &&
2752  "We shouldn't generate an undefined shift!");
2753  return DAG.getNode(ISD::SRL, dl, VT, Q,
2754  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2755  } else {
2756  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2757  if (Created)
2758  Created->push_back(NPQ.getNode());
2759  NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2760  DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2761  if (Created)
2762  Created->push_back(NPQ.getNode());
2763  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2764  if (Created)
2765  Created->push_back(NPQ.getNode());
2766  return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2767  DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2768  }
2769 }
mu magicu(unsigned LeadingZeros=0) const
Definition: APInt.cpp:1440
const SDValue & getOperand(unsigned Num) const
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1703
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
APInt m
magic number
Definition: APInt.h:1704
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned s
shift amount
Definition: APInt.h:1706
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool a
add indicator
Definition: APInt.h:1705
bool PPCTargetLowering::CanLowerReturn ( CallingConv::ID  CallConv,
MachineFunction MF,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
LLVMContext Context 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 5016 of file PPCISelLowering.cpp.

5019  {
5021  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5022  RVLocs, Context);
5023  return CCInfo.CheckReturn(Outs, RetCC_PPC);
5024 }
const TargetMachine & getTargetMachine() const
bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtualinherited

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.

canOpTrap - Returns true if the operation can trap for the value type. VT must be a legal type.

Definition at line 869 of file TargetLoweringBase.cpp.

869  {
870  assert(isTypeLegal(VT));
871  switch (Op) {
872  default:
873  return false;
874  case ISD::FDIV:
875  case ISD::FREM:
876  case ISD::SDIV:
877  case ISD::UDIV:
878  case ISD::SREM:
879  case ISD::UREM:
880  return true;
881  }
882 }
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::clearOperationActions ( )
inlineprotectedinherited

Remove all operation actions.

Definition at line 1088 of file TargetLowering.h.

1088  {
1089  }
void llvm::TargetLoweringBase::clearRegisterClasses ( )
inlineprotectedinherited

Remove all register classes.

Definition at line 1081 of file TargetLowering.h.

1081  {
1082  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1083 
1084  AvailableRegClasses.clear();
1085  }
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void TargetLowering::ComputeConstraintToUse ( AsmOperandInfo OpInfo,
SDValue  Op,
SelectionDAG DAG = nullptr 
) const
virtualinherited

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

Definition at line 2582 of file TargetLowering.cpp.

2584  {
2585  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2586 
2587  // Single-letter constraints ('r') are very common.
2588  if (OpInfo.Codes.size() == 1) {
2589  OpInfo.ConstraintCode = OpInfo.Codes[0];
2590  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2591  } else {
2592  ChooseConstraint(OpInfo, *this, Op, DAG);
2593  }
2594 
2595  // 'X' matches anything.
2596  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2597  // Labels and constants are handled elsewhere ('X' is the only thing
2598  // that matches labels). For Functions, the type here is the type of
2599  // the result, which is not what we want to look at; leave them alone.
2600  Value *v = OpInfo.CallOperandVal;
2601  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2602  OpInfo.CallOperandVal = v;
2603  return;
2604  }
2605 
2606  // Otherwise, try to resolve it to something we know about by looking at
2607  // the actual operand type.
2608  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2609  OpInfo.ConstraintCode = Repl;
2610  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2611  }
2612  }
2613 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
assert(Globals.size() > 1)
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
LLVM Value Representation.
Definition: Value.h:69
void PPCTargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
APInt KnownZero,
APInt KnownOne,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 8764 of file PPCISelLowering.cpp.

8768  {
8769  KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8770  switch (Op.getOpcode()) {
8771  default: break;
8772  case PPCISD::LBRX: {
8773  // lhbrx is known to have the top bits cleared out.
8774  if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8775  KnownZero = 0xFFFF0000;
8776  break;
8777  }
8778  case ISD::INTRINSIC_WO_CHAIN: {
8779  switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8780  default: break;
8781  case Intrinsic::ppc_altivec_vcmpbfp_p:
8782  case Intrinsic::ppc_altivec_vcmpeqfp_p:
8783  case Intrinsic::ppc_altivec_vcmpequb_p:
8784  case Intrinsic::ppc_altivec_vcmpequh_p:
8785  case Intrinsic::ppc_altivec_vcmpequw_p:
8786  case Intrinsic::ppc_altivec_vcmpgefp_p:
8787  case Intrinsic::ppc_altivec_vcmpgtfp_p:
8788  case Intrinsic::ppc_altivec_vcmpgtsb_p:
8789  case Intrinsic::ppc_altivec_vcmpgtsh_p:
8790  case Intrinsic::ppc_altivec_vcmpgtsw_p:
8791  case Intrinsic::ppc_altivec_vcmpgtub_p:
8792  case Intrinsic::ppc_altivec_vcmpgtuh_p:
8793  case Intrinsic::ppc_altivec_vcmpgtuw_p:
8794  KnownZero = ~1U; // All bits but the low one are known to be zero.
8795  break;
8796  }
8797  }
8798  }
8799 }
const SDValue & getOperand(unsigned i) const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
Class for arbitrary precision integers.
Definition: APInt.h:75
unsigned TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
const SelectionDAG DAG,
unsigned  Depth = 0 
) const
virtualinherited

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1104 of file TargetLowering.cpp.

1106  {
1110  Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1111  "Should use ComputeNumSignBits if you don't know whether Op"
1112  " is a target node!");
1113  return 1;
1114 }
assert(Globals.size() > 1)
unsigned getOpcode() const
void TargetLoweringBase::computeRegisterProperties ( )
protectedinherited

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1025 of file TargetLoweringBase.cpp.

1025  {
1027  "Too many value types for ValueTypeActions to hold!");
1028 
1029  // Everything defaults to needing one register.
1030  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1031  NumRegistersForVT[i] = 1;
1033  }
1034  // ...except isVoid, which doesn't need any registers.
1036 
1037  // Find the largest integer register class.
1038  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1039  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1040  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1041 
1042  // Every integer value type larger than this largest register takes twice as
1043  // many registers to represent as the previous ValueType.
1044  for (unsigned ExpandedReg = LargestIntReg + 1;
1045  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1046  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1047  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1048  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1051  }
1052 
1053  // Inspect all of the ValueType's smaller than the largest integer
1054  // register to see which ones need promotion.
1055  unsigned LegalIntReg = LargestIntReg;
1056  for (unsigned IntReg = LargestIntReg - 1;
1057  IntReg >= (unsigned)MVT::i1; --IntReg) {
1058  MVT IVT = (MVT::SimpleValueType)IntReg;
1059  if (isTypeLegal(IVT)) {
1060  LegalIntReg = IntReg;
1061  } else {
1062  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1063  (const MVT::SimpleValueType)LegalIntReg;
1065  }
1066  }
1067 
1068  // ppcf128 type is really two f64's.
1069  if (!isTypeLegal(MVT::ppcf128)) {
1074  }
1075 
1076  // Decide how to handle f128. If the target does not have native f128 support,
1077  // expand it to i128 and we will be generating soft float library calls.
1078  if (!isTypeLegal(MVT::f128)) {
1083  }
1084 
1085  // Decide how to handle f64. If the target does not have native f64 support,
1086  // expand it to i64 and we will be generating soft float library calls.
1087  if (!isTypeLegal(MVT::f64)) {
1092  }
1093 
1094  // Decide how to handle f32. If the target does not have native support for
1095  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1096  if (!isTypeLegal(MVT::f32)) {
1097  if (isTypeLegal(MVT::f64)) {
1102  } else {
1107  }
1108  }
1109 
1110  if (!isTypeLegal(MVT::f16)) {
1115  }
1116 
1117  // Loop over all of the vector value types to see which need transformations.
1118  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1119  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1120  MVT VT = (MVT::SimpleValueType) i;
1121  if (isTypeLegal(VT))
1122  continue;
1123 
1124  MVT EltVT = VT.getVectorElementType();
1125  unsigned NElts = VT.getVectorNumElements();
1126  bool IsLegalWiderType = false;
1127  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1128  switch (PreferredAction) {
1129  case TypePromoteInteger: {
1130  // Try to promote the elements of integer vectors. If no legal
1131  // promotion was found, fall through to the widen-vector method.
1132  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1133  MVT SVT = (MVT::SimpleValueType) nVT;
1134  // Promote vectors of integers to vectors with the same number
1135  // of elements, with a wider element type.
1136  if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1137  && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1138  && SVT.getScalarType().isInteger()) {
1139  TransformToType[i] = SVT;
1140  RegisterTypeForVT[i] = SVT;
1141  NumRegistersForVT[i] = 1;
1143  IsLegalWiderType = true;
1144  break;
1145  }
1146  }
1147  if (IsLegalWiderType)
1148  break;
1149  }
1150  case TypeWidenVector: {
1151  // Try to widen the vector.
1152  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1153  MVT SVT = (MVT::SimpleValueType) nVT;
1154  if (SVT.getVectorElementType() == EltVT
1155  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1156  TransformToType[i] = SVT;
1157  RegisterTypeForVT[i] = SVT;
1158  NumRegistersForVT[i] = 1;
1160  IsLegalWiderType = true;
1161  break;
1162  }
1163  }
1164  if (IsLegalWiderType)
1165  break;
1166  }
1167  case TypeSplitVector:
1168  case TypeScalarizeVector: {
1169  MVT IntermediateVT;
1170  MVT RegisterVT;
1171  unsigned NumIntermediates;
1172  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1173  NumIntermediates, RegisterVT, this);
1174  RegisterTypeForVT[i] = RegisterVT;
1175 
1176  MVT NVT = VT.getPow2VectorType();
1177  if (NVT == VT) {
1178  // Type is already a power of 2. The default action is to split.
1180  if (PreferredAction == TypeScalarizeVector)
1182  else
1184  } else {
1185  TransformToType[i] = NVT;
1187  }
1188  break;
1189  }
1190  default:
1191  llvm_unreachable("Unknown vector legalization action!");
1192  }
1193  }
1194 
1195  // Determine the 'representative' register class for each value type.
1196  // An representative register class is the largest (meaning one which is
1197  // not a sub-register class / subreg register class) legal register class for
1198  // a group of value types. For example, on i386, i8, i16, and i32
1199  // representative would be GR32; while on x86_64 it's GR64.
1200  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1201  const TargetRegisterClass* RRC;
1202  uint8_t Cost;
1203  std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1204  RepRegClassForVT[i] = RRC;
1205  RepRegClassCostForVT[i] = Cost;
1206  }
1207 }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
MVT TransformToType[MVT::LAST_VALUETYPE]
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MVT getScalarType() const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
unsigned getVectorNumElements() const
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Y = RRC X, rotate right via carry.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
void setTypeAction(MVT VT, LegalizeTypeAction Action)
MVT getPow2VectorType() const
MVT getVectorElementType() const
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
FastISel * PPCTargetLowering::createFastISel ( FunctionLoweringInfo FuncInfo,
const TargetLibraryInfo LibInfo 
) const
overridevirtual

createFastISel - This method returns a target-specific FastISel object, or null if the target does not support "fast" instruction selection.

Reimplemented from llvm::TargetLowering.

Definition at line 9273 of file PPCISelLowering.cpp.

9274  {
9275  return PPC::createFastISel(FuncInfo, LibInfo);
9276 }
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
SDValue PPCTargetLowering::createMemcpyOutsideCallSeq ( SDValue  Arg,
SDValue  PtrOff,
SDValue  CallSeqStart,
ISD::ArgFlagsTy  Flags,
SelectionDAG DAG,
SDLoc  dl 
) const
private

Definition at line 4130 of file PPCISelLowering.cpp.

4134  {
4135  SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4136  CallSeqStart.getNode()->getOperand(0),
4137  Flags, DAG, dl);
4138  // The MEMCPY must go outside the CALLSEQ_START..END.
4139  SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4140  CallSeqStart.getNode()->getOperand(1),
4141  SDLoc(MemcpyCall));
4142  DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4143  NewCallSeqStart.getNode());
4144  return NewCallSeqStart;
4145 }
const SDValue & getOperand(unsigned Num) const
SDNode * getNode() const
get the SDNode which holds the desired result
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
SDValue PPCTargetLowering::DAGCombineExtBoolTrunc ( SDNode N,
DAGCombinerInfo DCI 
) const
private

Definition at line 7927 of file PPCISelLowering.cpp.

7928  {
7929  SelectionDAG &DAG = DCI.DAG;
7930  SDLoc dl(N);
7931 
7932  // If we're tracking CR bits, we need to be careful that we don't have:
7933  // zext(binary-ops(trunc(x), trunc(y)))
7934  // or
7935  // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7936  // such that we're unnecessarily moving things into CR bits that can more
7937  // efficiently stay in GPRs. Note that if we're not certain that the high
7938  // bits are set as required by the final extension, we still may need to do
7939  // some masking to get the proper behavior.
7940 
7941  // This same functionality is important on PPC64 when dealing with
7942  // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7943  // the return values of functions. Because it is so similar, it is handled
7944  // here as well.
7945 
7946  if (N->getValueType(0) != MVT::i32 &&
7947  N->getValueType(0) != MVT::i64)
7948  return SDValue();
7949 
7950  if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7951  Subtarget.useCRBits()) ||
7952  (N->getOperand(0).getValueType() == MVT::i32 &&
7953  Subtarget.isPPC64())))
7954  return SDValue();
7955 
7956  if (N->getOperand(0).getOpcode() != ISD::AND &&
7957  N->getOperand(0).getOpcode() != ISD::OR &&
7958  N->getOperand(0).getOpcode() != ISD::XOR &&
7959  N->getOperand(0).getOpcode() != ISD::SELECT &&
7960  N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7961  return SDValue();
7962 
7963  SmallVector<SDValue, 4> Inputs;
7964  SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7965  SmallPtrSet<SDNode *, 16> Visited;
7966 
7967  // Visit all inputs, collect all binary operations (and, or, xor and
7968  // select) that are all fed by truncations.
7969  while (!BinOps.empty()) {
7970  SDValue BinOp = BinOps.back();
7971  BinOps.pop_back();
7972 
7973  if (!Visited.insert(BinOp.getNode()))
7974  continue;
7975 
7976  PromOps.push_back(BinOp);
7977 
7978  for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7979  // The condition of the select is not promoted.
7980  if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7981  continue;
7982  if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7983  continue;
7984 
7985  if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7986  isa<ConstantSDNode>(BinOp.getOperand(i))) {
7987  Inputs.push_back(BinOp.getOperand(i));
7988  } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7989  BinOp.getOperand(i).getOpcode() == ISD::OR ||
7990  BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7991  BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7992  BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7993  BinOps.push_back(BinOp.getOperand(i));
7994  } else {
7995  // We have an input that is not a truncation or another binary
7996  // operation; we'll abort this transformation.
7997  return SDValue();
7998  }
7999  }
8000  }
8001 
8002  // Make sure that this is a self-contained cluster of operations (which
8003  // is not quite the same thing as saying that everything has only one
8004  // use).
8005  for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8006  if (isa<ConstantSDNode>(Inputs[i]))
8007  continue;
8008 
8009  for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8010  UE = Inputs[i].getNode()->use_end();
8011  UI != UE; ++UI) {
8012  SDNode *User = *UI;
8013  if (User != N && !Visited.count(User))
8014  return SDValue();
8015 
8016  // Make sure that we're not going to promote the non-output-value
8017  // operand(s) or SELECT or SELECT_CC.
8018  // FIXME: Although we could sometimes handle this, and it does occur in
8019  // practice that one of the condition inputs to the select is also one of
8020  // the outputs, we currently can't deal with this.
8021  if (User->getOpcode() == ISD::SELECT) {
8022  if (User->getOperand(0) == Inputs[i])
8023  return SDValue();
8024  } else if (User->getOpcode() == ISD::SELECT_CC) {
8025  if (User->getOperand(0) == Inputs[i] ||
8026  User->getOperand(1) == Inputs[i])
8027  return SDValue();
8028  }
8029  }
8030  }
8031 
8032  for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8033  for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8034  UE = PromOps[i].getNode()->use_end();
8035  UI != UE; ++UI) {
8036  SDNode *User = *UI;
8037  if (User != N && !Visited.count(User))
8038  return SDValue();
8039 
8040  // Make sure that we're not going to promote the non-output-value
8041  // operand(s) or SELECT or SELECT_CC.
8042  // FIXME: Although we could sometimes handle this, and it does occur in
8043  // practice that one of the condition inputs to the select is also one of
8044  // the outputs, we currently can't deal with this.
8045  if (User->getOpcode() == ISD::SELECT) {
8046  if (User->getOperand(0) == PromOps[i])
8047  return SDValue();
8048  } else if (User->getOpcode() == ISD::SELECT_CC) {
8049  if (User->getOperand(0) == PromOps[i] ||
8050  User->getOperand(1) == PromOps[i])
8051  return SDValue();
8052  }
8053  }
8054  }
8055 
8056  unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8057  bool ReallyNeedsExt = false;
8058  if (N->getOpcode() != ISD::ANY_EXTEND) {
8059  // If all of the inputs are not already sign/zero extended, then
8060  // we'll still need to do that at the end.
8061  for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8062  if (isa<ConstantSDNode>(Inputs[i]))
8063  continue;
8064 
8065  unsigned OpBits =
8066  Inputs[i].getOperand(0).getValueSizeInBits();
8067  assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8068 
8069  if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8070  !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8071  APInt::getHighBitsSet(OpBits,
8072  OpBits-PromBits))) ||
8073  (N->getOpcode() == ISD::SIGN_EXTEND &&
8074  DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8075  (OpBits-(PromBits-1)))) {
8076  ReallyNeedsExt = true;
8077  break;
8078  }
8079  }
8080  }
8081 
8082  // Replace all inputs, either with the truncation operand, or a
8083  // truncation or extension to the final output type.
8084  for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8085  // Constant inputs need to be replaced with the to-be-promoted nodes that
8086  // use them because they might have users outside of the cluster of
8087  // promoted nodes.
8088  if (isa<ConstantSDNode>(Inputs[i]))
8089  continue;
8090 
8091  SDValue InSrc = Inputs[i].getOperand(0);
8092  if (Inputs[i].getValueType() == N->getValueType(0))
8093  DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8094  else if (N->getOpcode() == ISD::SIGN_EXTEND)
8095  DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8096  DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8097  else if (N->getOpcode() == ISD::ZERO_EXTEND)
8098  DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8099  DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8100  else
8101  DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8102  DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8103  }
8104 
8105  // Replace all operations (these are all the same, but have a different
8106  // (promoted) return type). DAG.getNode will validate that the types of
8107  // a binary operator match, so go through the list in reverse so that
8108  // we've likely promoted both operands first.
8109  while (!PromOps.empty()) {
8110  SDValue PromOp = PromOps.back();
8111  PromOps.pop_back();
8112 
8113  unsigned C;
8114  switch (PromOp.getOpcode()) {
8115  default: C = 0; break;
8116  case ISD::SELECT: C = 1; break;
8117  case ISD::SELECT_CC: C = 2; break;
8118  }
8119 
8120  if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8121  PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8122  (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8123  PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8124  // The to-be-promoted operands of this node have not yet been
8125  // promoted (this should be rare because we're going through the
8126  // list backward, but if one of the operands has several users in
8127  // this cluster of to-be-promoted nodes, it is possible).
8128  PromOps.insert(PromOps.begin(), PromOp);
8129  continue;
8130  }
8131 
8132  SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8133  PromOp.getNode()->op_end());
8134 
8135  // If this node has constant inputs, then they'll need to be promoted here.
8136  for (unsigned i = 0; i < 2; ++i) {
8137  if (!isa<ConstantSDNode>(Ops[C+i]))
8138  continue;
8139  if (Ops[C+i].getValueType() == N->getValueType(0))
8140  continue;
8141 
8142  if (N->getOpcode() == ISD::SIGN_EXTEND)
8143  Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8144  else if (N->getOpcode() == ISD::ZERO_EXTEND)
8145  Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8146  else
8147  Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8148  }
8149 
8150  DAG.ReplaceAllUsesOfValueWith(PromOp,
8151  DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8152  }
8153 
8154  // Now we're left with the initial extension itself.
8155  if (!ReallyNeedsExt)
8156  return N->getOperand(0);
8157 
8158  // To zero extend, just mask off everything except for the first bit (in the
8159  // i1 case).
8160  if (N->getOpcode() == ISD::ZERO_EXTEND)
8161  return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8163  N->getValueSizeInBits(0), PromBits),
8164  N->getValueType(0)));
8165 
8166  assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8167  "Invalid extension type");
8168  EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8169  SDValue ShiftCst =
8170  DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8171  return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8172  DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8173  N->getOperand(0), ShiftCst), ShiftCst);
8174 }
unsigned getValueSizeInBits(unsigned ResNo) const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
unsigned getOpcode() const
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
const SDValue & getOperand(unsigned Num) const
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
const PPCSubtarget & Subtarget
SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
unsigned getOpcode() const
use_iterator use_begin() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
op_iterator op_begin() const
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:476
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
op_iterator op_end() const
bool useCRBits() const
Definition: PPCSubtarget.h:181
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue PPCTargetLowering::DAGCombineFastRecip ( SDValue  Op,
DAGCombinerInfo DCI 
) const
private

Definition at line 7405 of file PPCISelLowering.cpp.

7406  {
7407  if (DCI.isAfterLegalizeVectorOps())
7408  return SDValue();
7409 
7410  EVT VT = Op.getValueType();
7411 
7412  if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7413  (VT == MVT::f64 && Subtarget.hasFRE()) ||
7414  (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7415  (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7416 
7417  // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7418  // For the reciprocal, we need to find the zero of the function:
7419  // F(X) = A X - 1 [which has a zero at X = 1/A]
7420  // =>
7421  // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7422  // does not require additional intermediate precision]
7423 
7424  // Convergence is quadratic, so we essentially double the number of digits
7425  // correct after every iteration. The minimum architected relative
7426  // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7427  // 23 digits and double has 52 digits.
7428  int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7429  if (VT.getScalarType() == MVT::f64)
7430  ++Iterations;
7431 
7432  SelectionDAG &DAG = DCI.DAG;
7433  SDLoc dl(Op);
7434 
7435  SDValue FPOne =
7436  DAG.getConstantFP(1.0, VT.getScalarType());
7437  if (VT.isVector()) {
7438  assert(VT.getVectorNumElements() == 4 &&
7439  "Unknown vector type");
7440  FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7441  FPOne, FPOne, FPOne, FPOne);
7442  }
7443 
7444  SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7445  DCI.AddToWorklist(Est.getNode());
7446 
7447  // Newton iterations: Est = Est + Est (1 - Arg * Est)
7448  for (int i = 0; i < Iterations; ++i) {
7449  SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7450  DCI.AddToWorklist(NewEst.getNode());
7451 
7452  NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7453  DCI.AddToWorklist(NewEst.getNode());
7454 
7455  NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7456  DCI.AddToWorklist(NewEst.getNode());
7457 
7458  Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7459  DCI.AddToWorklist(Est.getNode());
7460  }
7461 
7462  return Est;
7463  }
7464 
7465  return SDValue();
7466 }
bool hasAltivec() const
Definition: PPCSubtarget.h:207
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT getScalarType() const
Definition: ValueTypes.h:211
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
const PPCSubtarget & Subtarget
Reciprocal estimate instructions (unary FP ops).
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
bool hasRecipPrec() const
Definition: PPCSubtarget.h:202
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool hasVSX() const
Definition: PPCSubtarget.h:209
EVT getValueType() const
bool hasFRES() const
Definition: PPCSubtarget.h:199
bool hasFRE() const
Definition: PPCSubtarget.h:198
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT ( SDValue  Op,
DAGCombinerInfo DCI 
) const
private

Definition at line 7468 of file PPCISelLowering.cpp.

7469  {
7470  if (DCI.isAfterLegalizeVectorOps())
7471  return SDValue();
7472 
7473  EVT VT = Op.getValueType();
7474 
7475  if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7476  (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7477  (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7478  (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7479 
7480  // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7481  // For the reciprocal sqrt, we need to find the zero of the function:
7482  // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7483  // =>
7484  // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7485  // As a result, we precompute A/2 prior to the iteration loop.
7486 
7487  // Convergence is quadratic, so we essentially double the number of digits
7488  // correct after every iteration. The minimum architected relative
7489  // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7490  // 23 digits and double has 52 digits.
7491  int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7492  if (VT.getScalarType() == MVT::f64)
7493  ++Iterations;
7494 
7495  SelectionDAG &DAG = DCI.DAG;
7496  SDLoc dl(Op);
7497 
7498  SDValue FPThreeHalves =
7499  DAG.getConstantFP(1.5, VT.getScalarType());
7500  if (VT.isVector()) {
7501  assert(VT.getVectorNumElements() == 4 &&
7502  "Unknown vector type");
7503  FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7504  FPThreeHalves, FPThreeHalves,
7505  FPThreeHalves, FPThreeHalves);
7506  }
7507 
7508  SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7509  DCI.AddToWorklist(Est.getNode());
7510 
7511  // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7512  // this entire sequence requires only one FP constant.
7513  SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7514  DCI.AddToWorklist(HalfArg.getNode());
7515 
7516  HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7517  DCI.AddToWorklist(HalfArg.getNode());
7518 
7519  // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7520  for (int i = 0; i < Iterations; ++i) {
7521  SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7522  DCI.AddToWorklist(NewEst.getNode());
7523 
7524  NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7525  DCI.AddToWorklist(NewEst.getNode());
7526 
7527  NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7528  DCI.AddToWorklist(NewEst.getNode());
7529 
7530  Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7531  DCI.AddToWorklist(Est.getNode());
7532  }
7533 
7534  return Est;
7535  }
7536 
7537  return SDValue();
7538 }
bool hasAltivec() const
Definition: PPCSubtarget.h:207
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT getScalarType() const
Definition: ValueTypes.h:211
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
const PPCSubtarget & Subtarget
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool hasRecipPrec() const
Definition: PPCSubtarget.h:202
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool hasVSX() const
Definition: PPCSubtarget.h:209
EVT getValueType() const
bool hasFRSQRTE() const
Definition: PPCSubtarget.h:200
bool hasFRSQRTES() const
Definition: PPCSubtarget.h:201
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue PPCTargetLowering::DAGCombineTruncBoolExt ( SDNode N,
DAGCombinerInfo DCI 
) const
private

Definition at line 7648 of file PPCISelLowering.cpp.

7649  {
7650  SelectionDAG &DAG = DCI.DAG;
7651  SDLoc dl(N);
7652 
7654  "Expecting to be tracking CR bits");
7655  // If we're tracking CR bits, we need to be careful that we don't have:
7656  // trunc(binary-ops(zext(x), zext(y)))
7657  // or
7658  // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7659  // such that we're unnecessarily moving things into GPRs when it would be
7660  // better to keep them in CR bits.
7661 
7662  // Note that trunc here can be an actual i1 trunc, or can be the effective
7663  // truncation that comes from a setcc or select_cc.
7664  if (N->getOpcode() == ISD::TRUNCATE &&
7665  N->getValueType(0) != MVT::i1)
7666  return SDValue();
7667 
7668  if (N->getOperand(0).getValueType() != MVT::i32 &&
7669  N->getOperand(0).getValueType() != MVT::i64)
7670  return SDValue();
7671 
7672  if (N->getOpcode() == ISD::SETCC ||
7673  N->getOpcode() == ISD::SELECT_CC) {
7674  // If we're looking at a comparison, then we need to make sure that the
7675  // high bits (all except for the first) don't matter the result.
7676  ISD::CondCode CC =
7677  cast<CondCodeSDNode>(N->getOperand(
7678  N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7679  unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7680 
7681  if (ISD::isSignedIntSetCC(CC)) {
7682  if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7683  DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7684  return SDValue();
7685  } else if (ISD::isUnsignedIntSetCC(CC)) {
7686  if (!DAG.MaskedValueIsZero(N->getOperand(0),
7687  APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7688  !DAG.MaskedValueIsZero(N->getOperand(1),
7689  APInt::getHighBitsSet(OpBits, OpBits-1)))
7690  return SDValue();
7691  } else {
7692  // This is neither a signed nor an unsigned comparison, just make sure
7693  // that the high bits are equal.
7694  APInt Op1Zero, Op1One;
7695  APInt Op2Zero, Op2One;
7696  DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7697  DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7698 
7699  // We don't really care about what is known about the first bit (if
7700  // anything), so clear it in all masks prior to comparing them.
7701  Op1Zero.clearBit(0); Op1One.clearBit(0);
7702  Op2Zero.clearBit(0); Op2One.clearBit(0);
7703 
7704  if (Op1Zero != Op2Zero || Op1One != Op2One)
7705  return SDValue();
7706  }
7707  }
7708 
7709  // We now know that the higher-order bits are irrelevant, we just need to
7710  // make sure that all of the intermediate operations are bit operations, and
7711  // all inputs are extensions.
7712  if (N->getOperand(0).getOpcode() != ISD::AND &&
7713  N->getOperand(0).getOpcode() != ISD::OR &&
7714  N->getOperand(0).getOpcode() != ISD::XOR &&
7715  N->getOperand(0).getOpcode() != ISD::SELECT &&
7716  N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7717  N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7718  N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7719  N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7721  return SDValue();
7722 
7723  if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7724  N->getOperand(1).getOpcode() != ISD::AND &&
7725  N->getOperand(1).getOpcode() != ISD::OR &&
7726  N->getOperand(1).getOpcode() != ISD::XOR &&
7727  N->getOperand(1).getOpcode() != ISD::SELECT &&
7728  N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7729  N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7730  N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7731  N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7733  return SDValue();
7734 
7735  SmallVector<SDValue, 4> Inputs;
7736  SmallVector<SDValue, 8> BinOps, PromOps;
7737  SmallPtrSet<SDNode *, 16> Visited;
7738 
7739  for (unsigned i = 0; i < 2; ++i) {
7740  if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7741  N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7742  N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7743  N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7744  isa<ConstantSDNode>(N->getOperand(i)))
7745  Inputs.push_back(N->getOperand(i));
7746  else
7747  BinOps.push_back(N->getOperand(i));
7748 
7749  if (N->getOpcode() == ISD::TRUNCATE)
7750  break;
7751  }
7752 
7753  // Visit all inputs, collect all binary operations (and, or, xor and
7754  // select) that are all fed by extensions.
7755  while (!BinOps.empty()) {
7756  SDValue BinOp = BinOps.back();
7757  BinOps.pop_back();
7758 
7759  if (!Visited.insert(BinOp.getNode()))
7760  continue;
7761 
7762  PromOps.push_back(BinOp);
7763 
7764  for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7765  // The condition of the select is not promoted.
7766  if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7767  continue;
7768  if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7769  continue;
7770 
7771  if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7772  BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7773  BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7774  BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7775  isa<ConstantSDNode>(BinOp.getOperand(i))) {
7776  Inputs.push_back(BinOp.getOperand(i));
7777  } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7778  BinOp.getOperand(i).getOpcode() == ISD::OR ||
7779  BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7780  BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7781  BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7782  BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7783  BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7784  BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7785  BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7786  BinOps.push_back(BinOp.getOperand(i));
7787  } else {
7788  // We have an input that is not an extension or another binary
7789  // operation; we'll abort this transformation.
7790  return SDValue();
7791  }
7792  }
7793  }
7794 
7795  // Make sure that this is a self-contained cluster of operations (which
7796  // is not quite the same thing as saying that everything has only one
7797  // use).
7798  for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7799  if (isa<ConstantSDNode>(Inputs[i]))
7800  continue;
7801 
7802  for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7803  UE = Inputs[i].getNode()->use_end();
7804  UI != UE; ++UI) {
7805  SDNode *User = *UI;
7806  if (User != N && !Visited.count(User))
7807  return SDValue();
7808 
7809  // Make sure that we're not going to promote the non-output-value
7810  // operand(s) or SELECT or SELECT_CC.
7811  // FIXME: Although we could sometimes handle this, and it does occur in
7812  // practice that one of the condition inputs to the select is also one of
7813  // the outputs, we currently can't deal with this.
7814  if (User->getOpcode() == ISD::SELECT) {
7815  if (User->getOperand(0) == Inputs[i])
7816  return SDValue();
7817  } else if (User->getOpcode() == ISD::SELECT_CC) {
7818  if (User->getOperand(0) == Inputs[i] ||
7819  User->getOperand(1) == Inputs[i])
7820  return SDValue();
7821  }
7822  }
7823  }
7824 
7825  for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7826  for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7827  UE = PromOps[i].getNode()->use_end();
7828  UI != UE; ++UI) {
7829  SDNode *User = *UI;
7830  if (User != N && !Visited.count(User))
7831  return SDValue();
7832 
7833  // Make sure that we're not going to promote the non-output-value
7834  // operand(s) or SELECT or SELECT_CC.
7835  // FIXME: Although we could sometimes handle this, and it does occur in
7836  // practice that one of the condition inputs to the select is also one of
7837  // the outputs, we currently can't deal with this.
7838  if (User->getOpcode() == ISD::SELECT) {
7839  if (User->getOperand(0) == PromOps[i])
7840  return SDValue();
7841  } else if (User->getOpcode() == ISD::SELECT_CC) {
7842  if (User->getOperand(0) == PromOps[i] ||
7843  User->getOperand(1) == PromOps[i])
7844  return SDValue();
7845  }
7846  }
7847  }
7848 
7849  // Replace all inputs with the extension operand.
7850  for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7851  // Constants may have users outside the cluster of to-be-promoted nodes,
7852  // and so we need to replace those as we do the promotions.
7853  if (isa<ConstantSDNode>(Inputs[i]))
7854  continue;
7855  else
7856  DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7857  }
7858 
7859  // Replace all operations (these are all the same, but have a different
7860  // (i1) return type). DAG.getNode will validate that the types of
7861  // a binary operator match, so go through the list in reverse so that
7862  // we've likely promoted both operands first. Any intermediate truncations or
7863  // extensions disappear.
7864  while (!PromOps.empty()) {
7865  SDValue PromOp = PromOps.back();
7866  PromOps.pop_back();
7867 
7868  if (PromOp.getOpcode() == ISD::TRUNCATE ||
7869  PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7870  PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7871  PromOp.getOpcode() == ISD::ANY_EXTEND) {
7872  if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7873  PromOp.getOperand(0).getValueType() != MVT::i1) {
7874  // The operand is not yet ready (see comment below).
7875  PromOps.insert(PromOps.begin(), PromOp);
7876  continue;
7877  }
7878 
7879  SDValue RepValue = PromOp.getOperand(0);
7880  if (isa<ConstantSDNode>(RepValue))
7881  RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7882 
7883  DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7884  continue;
7885  }
7886 
7887  unsigned C;
7888  switch (PromOp.getOpcode()) {
7889  default: C = 0; break;
7890  case ISD::SELECT: C = 1; break;
7891  case ISD::SELECT_CC: C = 2; break;
7892  }
7893 
7894  if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7895  PromOp.getOperand(C).getValueType() != MVT::i1) ||
7896  (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7897  PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7898  // The to-be-promoted operands of this node have not yet been
7899  // promoted (this should be rare because we're going through the
7900  // list backward, but if one of the operands has several users in
7901  // this cluster of to-be-promoted nodes, it is possible).
7902  PromOps.insert(PromOps.begin(), PromOp);
7903  continue;
7904  }
7905 
7906  SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7907  PromOp.getNode()->op_end());
7908 
7909  // If there are any constant inputs, make sure they're replaced now.
7910  for (unsigned i = 0; i < 2; ++i)
7911  if (isa<ConstantSDNode>(Ops[C+i]))
7912  Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7913 
7914  DAG.ReplaceAllUsesOfValueWith(PromOp,
7915  DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7916  }
7917 
7918  // Now we're left with the initial truncation itself.
7919  if (N->getOpcode() == ISD::TRUNCATE)
7920  return N->getOperand(0);
7921 
7922  // Otherwise, this is a comparison. The operands to be compared have just
7923  // changed type (to i1), but everything else is the same.
7924  return SDValue(N, 0);
7925 }
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:267
unsigned getOpcode() const
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:256
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
const SDValue & getOperand(unsigned Num) const
bool isUnsignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:802
EVT getValueType(unsigned ResNo) const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const PPCSubtarget & Subtarget
bool isSignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:796
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Class for arbitrary precision integers.
Definition: APInt.h:75
op_iterator op_begin() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:476
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
void clearBit(unsigned bitPosition)
Set a given bit to 0.
Definition: APInt.cpp:593
op_iterator op_end() const
bool useCRBits() const
Definition: PPCSubtarget.h:181
EVT getValueType() const
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
MachineBasicBlock * PPCTargetLowering::EmitAtomicBinary ( MachineInstr MI,
MachineBasicBlock MBB,
bool  is64Bit,
unsigned  BinOpcode 
) const

Definition at line 6524 of file PPCISelLowering.cpp.

6525  {
6526  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6528 
6529  const BasicBlock *LLVM_BB = BB->getBasicBlock();
6530  MachineFunction *F = BB->getParent();
6531  MachineFunction::iterator It = BB;
6532  ++It;
6533 
6534  unsigned dest = MI->getOperand(0).getReg();
6535  unsigned ptrA = MI->getOperand(1).getReg();
6536  unsigned ptrB = MI->getOperand(2).getReg();
6537  unsigned incr = MI->getOperand(3).getReg();
6538  DebugLoc dl = MI->getDebugLoc();
6539 
6540  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6541  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6542  F->insert(It, loopMBB);
6543  F->insert(It, exitMBB);
6544  exitMBB->splice(exitMBB->begin(), BB,
6545  std::next(MachineBasicBlock::iterator(MI)), BB->end());
6546  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6547 
6548  MachineRegisterInfo &RegInfo = F->getRegInfo();
6549  unsigned TmpReg = (!BinOpcode) ? incr :
6550  RegInfo.createVirtualRegister(
6551  is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6552  (const TargetRegisterClass *) &PPC::GPRCRegClass);
6553 
6554  // thisMBB:
6555  // ...
6556  // fallthrough --> loopMBB
6557  BB->addSuccessor(loopMBB);
6558 
6559  // loopMBB:
6560  // l[wd]arx dest, ptr
6561  // add r0, dest, incr
6562  // st[wd]cx. r0, ptr
6563  // bne- loopMBB
6564  // fallthrough --> exitMBB
6565  BB = loopMBB;
6566  BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6567  .addReg(ptrA).addReg(ptrB);
6568  if (BinOpcode)
6569  BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6570  BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6571  .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6572  BuildMI(BB, dl, TII->get(PPC::BCC))
6573  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6574  BB->addSuccessor(loopMBB);
6575  BB->addSuccessor(exitMBB);
6576 
6577  // exitMBB:
6578  // ...
6579  BB = exitMBB;
6580  return BB;
6581 }
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
F(f)
const HexagonInstrInfo * TII
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * PPCTargetLowering::emitEHSjLjLongJmp ( MachineInstr MI,
MachineBasicBlock MBB 
) const

Definition at line 6862 of file PPCISelLowering.cpp.

6863  {
6864  DebugLoc DL = MI->getDebugLoc();
6866 
6867  MachineFunction *MF = MBB->getParent();
6868  MachineRegisterInfo &MRI = MF->getRegInfo();
6869 
6870  // Memory Reference
6873 
6874  MVT PVT = getPointerTy();
6875  assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6876  "Invalid Pointer Size!");
6877 
6878  const TargetRegisterClass *RC =
6879  (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6880  unsigned Tmp = MRI.createVirtualRegister(RC);
6881  // Since FP is only updated here but NOT referenced, it's treated as GPR.
6882  unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6883  unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6884  unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6885  (Subtarget.isSVR4ABI() &&
6887  PPC::R29 : PPC::R30);
6888 
6889  MachineInstrBuilder MIB;
6890 
6891  const int64_t LabelOffset = 1 * PVT.getStoreSize();
6892  const int64_t SPOffset = 2 * PVT.getStoreSize();
6893  const int64_t TOCOffset = 3 * PVT.getStoreSize();
6894  const int64_t BPOffset = 4 * PVT.getStoreSize();
6895 
6896  unsigned BufReg = MI->getOperand(0).getReg();
6897 
6898  // Reload FP (the jumped-to function may not have had a
6899  // frame pointer, and if so, then its r31 will be restored
6900  // as necessary).
6901  if (PVT == MVT::i64) {
6902  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6903  .addImm(0)
6904  .addReg(BufReg);
6905  } else {
6906  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6907  .addImm(0)
6908  .addReg(BufReg);
6909  }
6910  MIB.setMemRefs(MMOBegin, MMOEnd);
6911 
6912  // Reload IP
6913  if (PVT == MVT::i64) {
6914  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6915  .addImm(LabelOffset)
6916  .addReg(BufReg);
6917  } else {
6918  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6919  .addImm(LabelOffset)
6920  .addReg(BufReg);
6921  }
6922  MIB.setMemRefs(MMOBegin, MMOEnd);
6923 
6924  // Reload SP
6925  if (PVT == MVT::i64) {
6926  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6927  .addImm(SPOffset)
6928  .addReg(BufReg);
6929  } else {
6930  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6931  .addImm(SPOffset)
6932  .addReg(BufReg);
6933  }
6934  MIB.setMemRefs(MMOBegin, MMOEnd);
6935 
6936  // Reload BP
6937  if (PVT == MVT::i64) {
6938  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6939  .addImm(BPOffset)
6940  .addReg(BufReg);
6941  } else {
6942  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6943  .addImm(BPOffset)
6944  .addReg(BufReg);
6945  }
6946  MIB.setMemRefs(MMOBegin, MMOEnd);
6947 
6948  // Reload TOC
6949  if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6950  MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6951  .addImm(TOCOffset)
6952  .addReg(BufReg);
6953 
6954  MIB.setMemRefs(MMOBegin, MMOEnd);
6955  }
6956 
6957  // Jump
6958  BuildMI(*MBB, MI, DL,
6959  TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6960  BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6961 
6962  MI->eraseFromParent();
6963  return MBB;
6964 }
const MachineFunction * getParent() const
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
const HexagonInstrInfo * TII
const DataLayout * DL
True if this is a little endian target.
unsigned getStoreSize() const
virtual MVT getPointerTy(uint32_t=0) const
const PPCSubtarget & Subtarget
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
assert(Globals.size() > 1)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
MachineRegisterInfo & getRegInfo()
const TargetMachine & getTarget() const
unsigned getReg() const
getReg - Returns the register number.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
llvm::MachineBasicBlock * PPCTargetLowering::emitEHSjLjSetJmp ( MachineInstr MI,
MachineBasicBlock MBB 
) const

Definition at line 6714 of file PPCISelLowering.cpp.

6715  {
6716  DebugLoc DL = MI->getDebugLoc();
6718 
6719  MachineFunction *MF = MBB->getParent();
6720  MachineRegisterInfo &MRI = MF->getRegInfo();
6721 
6722  const BasicBlock *BB = MBB->getBasicBlock();
6724  ++I;
6725 
6726  // Memory Reference
6729 
6730  unsigned DstReg = MI->getOperand(0).getReg();
6731  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6732  assert(RC->hasType(MVT::i32) && "Invalid destination!");
6733  unsigned mainDstReg = MRI.createVirtualRegister(RC);
6734  unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6735 
6736  MVT PVT = getPointerTy();
6737  assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6738  "Invalid Pointer Size!");
6739  // For v = setjmp(buf), we generate
6740  //
6741  // thisMBB:
6742  // SjLjSetup mainMBB
6743  // bl mainMBB
6744  // v_restore = 1
6745  // b sinkMBB
6746  //
6747  // mainMBB:
6748  // buf[LabelOffset] = LR
6749  // v_main = 0
6750  //
6751  // sinkMBB:
6752  // v = phi(main, restore)
6753  //
6754 
6755  MachineBasicBlock *thisMBB = MBB;
6756  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6757  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6758  MF->insert(I, mainMBB);
6759  MF->insert(I, sinkMBB);
6760 
6761  MachineInstrBuilder MIB;
6762 
6763  // Transfer the remainder of BB and its successor edges to sinkMBB.
6764  sinkMBB->splice(sinkMBB->begin(), MBB,
6766  sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6767 
6768  // Note that the structure of the jmp_buf used here is not compatible
6769  // with that used by libc, and is not designed to be. Specifically, it
6770  // stores only those 'reserved' registers that LLVM does not otherwise
6771  // understand how to spill. Also, by convention, by the time this
6772  // intrinsic is called, Clang has already stored the frame address in the
6773  // first slot of the buffer and stack address in the third. Following the
6774  // X86 target code, we'll store the jump address in the second slot. We also
6775  // need to save the TOC pointer (R2) to handle jumps between shared
6776  // libraries, and that will be stored in the fourth slot. The thread
6777  // identifier (R13) is not affected.
6778 
6779  // thisMBB:
6780  const int64_t LabelOffset = 1 * PVT.getStoreSize();
6781  const int64_t TOCOffset = 3 * PVT.getStoreSize();
6782  const int64_t BPOffset = 4 * PVT.getStoreSize();
6783 
6784  // Prepare IP either in reg.
6785  const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6786  unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6787  unsigned BufReg = MI->getOperand(1).getReg();
6788 
6789  if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6790  MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6791  .addReg(PPC::X2)
6792  .addImm(TOCOffset)
6793  .addReg(BufReg);
6794  MIB.setMemRefs(MMOBegin, MMOEnd);
6795  }
6796 
6797  // Naked functions never have a base pointer, and so we use r1. For all
6798  // other functions, this decision must be delayed until during PEI.
6799  unsigned BaseReg;
6800  if (MF->getFunction()->getAttributes().hasAttribute(
6802  BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6803  else
6804  BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6805 
6806  MIB = BuildMI(*thisMBB, MI, DL,
6807  TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6808  .addReg(BaseReg)
6809  .addImm(BPOffset)
6810  .addReg(BufReg);
6811  MIB.setMemRefs(MMOBegin, MMOEnd);
6812 
6813  // Setup
6814  MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6815  const PPCRegisterInfo *TRI =
6816  static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6817  MIB.addRegMask(TRI->getNoPreservedMask());
6818 
6819  BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6820 
6821  MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6822  .addMBB(mainMBB);
6823  MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6824 
6825  thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6826  thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6827 
6828  // mainMBB:
6829  // mainDstReg = 0
6830  MIB = BuildMI(mainMBB, DL,
6831  TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6832 
6833  // Store IP
6834  if (Subtarget.isPPC64()) {
6835  MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6836  .addReg(LabelReg)
6837  .addImm(LabelOffset)
6838  .addReg(BufReg);
6839  } else {
6840  MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6841  .addReg(LabelReg)
6842  .addImm(LabelOffset)
6843  .addReg(BufReg);
6844  }
6845 
6846  MIB.setMemRefs(MMOBegin, MMOEnd);
6847 
6848  BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6849  mainMBB->addSuccessor(sinkMBB);
6850 
6851  // sinkMBB:
6852  BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6853  TII->get(PPC::PHI), DstReg)
6854  .addReg(mainDstReg).addMBB(mainMBB)
6855  .addReg(restoreDstReg).addMBB(thisMBB);
6856 
6857  MI->eraseFromParent();
6858  return sinkMBB;
6859 }
const MachineFunction * getParent() const
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
Naked function.
Definition: Attributes.h:80
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:412
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClass(unsigned Reg) const
const DataLayout * DL
True if this is a little endian target.
unsigned getStoreSize() const
virtual MVT getPointerTy(uint32_t=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
const PPCSubtarget & Subtarget
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
const BasicBlock * getBasicBlock() const
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
assert(Globals.size() > 1)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getNoPreservedMask() const
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
bool isPPC64() const
Definition: PPCSubtarget.h:168
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
#define I(x, y, z)
Definition: MD5.cpp:54
virtual const TargetRegisterInfo * getRegisterInfo() const
bool hasType(EVT vt) const
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
MachineBasicBlock * PPCTargetLowering::EmitInstrWithCustomInserter ( MachineInstr MI,
MachineBasicBlock MBB 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 6967 of file PPCISelLowering.cpp.

6968  {
6969  if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6970  MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6971  return emitEHSjLjSetJmp(MI, BB);
6972  } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6973  MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6974  return emitEHSjLjLongJmp(MI, BB);
6975  }
6976 
6978 
6979  // To "insert" these instructions we actually have to insert their
6980  // control-flow patterns.
6981  const BasicBlock *LLVM_BB = BB->getBasicBlock();
6982  MachineFunction::iterator It = BB;
6983  ++It;
6984 
6985  MachineFunction *F = BB->getParent();
6986 
6987  if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6988  MI->getOpcode() == PPC::SELECT_CC_I8 ||
6989  MI->getOpcode() == PPC::SELECT_I4 ||
6990  MI->getOpcode() == PPC::SELECT_I8)) {
6992  if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6993  MI->getOpcode() == PPC::SELECT_CC_I8)
6994  Cond.push_back(MI->getOperand(4));
6995  else
6997  Cond.push_back(MI->getOperand(1));
6998 
6999  DebugLoc dl = MI->getDebugLoc();
7001  TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7002  Cond, MI->getOperand(2).getReg(),
7003  MI->getOperand(3).getReg());
7004  } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7005  MI->getOpcode() == PPC::SELECT_CC_I8 ||
7006  MI->getOpcode() == PPC::SELECT_CC_F4 ||
7007  MI->getOpcode() == PPC::SELECT_CC_F8 ||
7008  MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7009  MI->getOpcode() == PPC::SELECT_I4 ||
7010  MI->getOpcode() == PPC::SELECT_I8 ||
7011  MI->getOpcode() == PPC::SELECT_F4 ||
7012  MI->getOpcode() == PPC::SELECT_F8 ||
7013  MI->getOpcode() == PPC::SELECT_VRRC) {
7014  // The incoming instruction knows the destination vreg to set, the
7015  // condition code register to branch on, the true/false values to
7016  // select between, and a branch opcode to use.
7017 
7018  // thisMBB:
7019  // ...
7020  // TrueVal = ...
7021  // cmpTY ccX, r1, r2
7022  // bCC copy1MBB
7023  // fallthrough --> copy0MBB
7024  MachineBasicBlock *thisMBB = BB;
7025  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7026  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7027  DebugLoc dl = MI->getDebugLoc();
7028  F->insert(It, copy0MBB);
7029  F->insert(It, sinkMBB);
7030 
7031  // Transfer the remainder of BB and its successor edges to sinkMBB.
7032  sinkMBB->splice(sinkMBB->begin(), BB,
7033  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7034  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7035 
7036  // Next, add the true and fallthrough blocks as its successors.
7037  BB->addSuccessor(copy0MBB);
7038  BB->addSuccessor(sinkMBB);
7039 
7040  if (MI->getOpcode() == PPC::SELECT_I4 ||
7041  MI->getOpcode() == PPC::SELECT_I8 ||
7042  MI->getOpcode() == PPC::SELECT_F4 ||
7043  MI->getOpcode() == PPC::SELECT_F8 ||
7044  MI->getOpcode() == PPC::SELECT_VRRC) {
7045  BuildMI(BB, dl, TII->get(PPC::BC))
7046  .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7047  } else {
7048  unsigned SelectPred = MI->getOperand(4).getImm();
7049  BuildMI(BB, dl, TII->get(PPC::BCC))
7050  .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7051  }
7052 
7053  // copy0MBB:
7054  // %FalseValue = ...
7055  // # fallthrough to sinkMBB
7056  BB = copy0MBB;
7057 
7058  // Update machine-CFG edges
7059  BB->addSuccessor(sinkMBB);
7060 
7061  // sinkMBB:
7062  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7063  // ...
7064  BB = sinkMBB;
7065  BuildMI(*BB, BB->begin(), dl,
7066  TII->get(PPC::PHI), MI->getOperand(0).getReg())
7067  .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7068  .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7069  }
7070  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7071  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7072  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7073  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7074  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7075  BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7076  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7077  BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7078 
7079  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7080  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7081  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7082  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7083  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7084  BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7085  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7086  BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7087 
7088  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7089  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7090  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7091  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7092  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7093  BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7094  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7095  BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7096 
7097  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7098  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7099  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7100  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7101  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7102  BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7103  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7104  BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7105 
7106  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7107  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7108  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7109  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7110  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7111  BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7112  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7113  BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7114 
7115  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7116  BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7117  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7118  BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7119  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7120  BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7121  else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7122  BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7123 
7124  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7125  BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7126  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7127  BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7128  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7129  BB = EmitAtomicBinary(MI, BB, false, 0);
7130  else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7131  BB = EmitAtomicBinary(MI, BB, true, 0);
7132 
7133  else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7134  MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7135  bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7136 
7137  unsigned dest = MI->getOperand(0).getReg();
7138  unsigned ptrA = MI->getOperand(1).getReg();
7139  unsigned ptrB = MI->getOperand(2).getReg();
7140  unsigned oldval = MI->getOperand(3).getReg();
7141  unsigned newval = MI->getOperand(4).getReg();
7142  DebugLoc dl = MI->getDebugLoc();
7143 
7144  MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7145  MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7146  MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7147  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7148  F->insert(It, loop1MBB);
7149  F->insert(It, loop2MBB);
7150  F->insert(It, midMBB);
7151  F->insert(It, exitMBB);
7152  exitMBB->splice(exitMBB->begin(), BB,
7153  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7154  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7155 
7156  // thisMBB:
7157  // ...
7158  // fallthrough --> loopMBB
7159  BB->addSuccessor(loop1MBB);
7160 
7161  // loop1MBB:
7162  // l[wd]arx dest, ptr
7163  // cmp[wd] dest, oldval
7164  // bne- midMBB
7165  // loop2MBB:
7166  // st[wd]cx. newval, ptr
7167  // bne- loopMBB
7168  // b exitBB
7169  // midMBB:
7170  // st[wd]cx. dest, ptr
7171  // exitBB:
7172  BB = loop1MBB;
7173  BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7174  .addReg(ptrA).addReg(ptrB);
7175  BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7176  .addReg(oldval).addReg(dest);
7177  BuildMI(BB, dl, TII->get(PPC::BCC))
7178  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7179  BB->addSuccessor(loop2MBB);
7180  BB->addSuccessor(midMBB);
7181 
7182  BB = loop2MBB;
7183  BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7184  .addReg(newval).addReg(ptrA).addReg(ptrB);
7185  BuildMI(BB, dl, TII->get(PPC::BCC))
7186  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7187  BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7188  BB->addSuccessor(loop1MBB);
7189  BB->addSuccessor(exitMBB);
7190 
7191  BB = midMBB;
7192  BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7193  .addReg(dest).addReg(ptrA).addReg(ptrB);
7194  BB->addSuccessor(exitMBB);
7195 
7196  // exitMBB:
7197  // ...
7198  BB = exitMBB;
7199  } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7200  MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7201  // We must use 64-bit registers for addresses when targeting 64-bit,
7202  // since we're actually doing arithmetic on them. Other registers
7203  // can be 32-bit.
7204  bool is64bit = Subtarget.isPPC64();
7205  bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7206 
7207  unsigned dest = MI->getOperand(0).getReg();
7208  unsigned ptrA = MI->getOperand(1).getReg();
7209  unsigned ptrB = MI->getOperand(2).getReg();
7210  unsigned oldval = MI->getOperand(3).getReg();
7211  unsigned newval = MI->getOperand(4).getReg();
7212  DebugLoc dl = MI->getDebugLoc();
7213 
7214  MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7215  MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7216  MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7217  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7218  F->insert(It, loop1MBB);
7219  F->insert(It, loop2MBB);
7220  F->insert(It, midMBB);
7221  F->insert(It, exitMBB);
7222  exitMBB->splice(exitMBB->begin(), BB,
7223  std::next(MachineBasicBlock::iterator(MI)), BB->end());
7224  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7225 
7226  MachineRegisterInfo &RegInfo = F->getRegInfo();
7227  const TargetRegisterClass *RC =
7228  is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7229  (const TargetRegisterClass *) &PPC::GPRCRegClass;
7230  unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7231  unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7232  unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7233  unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7234  unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7235  unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7236  unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7237  unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7238  unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7239  unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7240  unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7241  unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7242  unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7243  unsigned Ptr1Reg;
7244  unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7245  unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7246  // thisMBB:
7247  // ...
7248  // fallthrough --> loopMBB
7249  BB->addSuccessor(loop1MBB);
7250 
7251  // The 4-byte load must be aligned, while a char or short may be
7252  // anywhere in the word. Hence all this nasty bookkeeping code.
7253  // add ptr1, ptrA, ptrB [copy if ptrA==0]
7254  // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7255  // xori shift, shift1, 24 [16]
7256  // rlwinm ptr, ptr1, 0, 0, 29
7257  // slw newval2, newval, shift
7258  // slw oldval2, oldval,shift
7259  // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7260  // slw mask, mask2, shift
7261  // and newval3, newval2, mask
7262  // and oldval3, oldval2, mask
7263  // loop1MBB:
7264  // lwarx tmpDest, ptr
7265  // and tmp, tmpDest, mask
7266  // cmpw tmp, oldval3
7267  // bne- midMBB
7268  // loop2MBB:
7269  // andc tmp2, tmpDest, mask
7270  // or tmp4, tmp2, newval3
7271  // stwcx. tmp4, ptr
7272  // bne- loop1MBB
7273  // b exitBB
7274  // midMBB:
7275  // stwcx. tmpDest, ptr
7276  // exitBB:
7277  // srw dest, tmpDest, shift
7278  if (ptrA != ZeroReg) {
7279  Ptr1Reg = RegInfo.createVirtualRegister(RC);
7280  BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7281  .addReg(ptrA).addReg(ptrB);
7282  } else {
7283  Ptr1Reg = ptrB;
7284  }
7285  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7286  .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7287  BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7288  .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7289  if (is64bit)
7290  BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7291  .addReg(Ptr1Reg).addImm(0).addImm(61);
7292  else
7293  BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7294  .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7295  BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7296  .addReg(newval).addReg(ShiftReg);
7297  BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7298  .addReg(oldval).addReg(ShiftReg);
7299  if (is8bit)
7300  BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7301  else {
7302  BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7303  BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7304  .addReg(Mask3Reg).addImm(65535);
7305  }
7306  BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7307  .addReg(Mask2Reg).addReg(ShiftReg);
7308  BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7309  .addReg(NewVal2Reg).addReg(MaskReg);
7310  BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7311  .addReg(OldVal2Reg).addReg(MaskReg);
7312 
7313  BB = loop1MBB;
7314  BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7315  .addReg(ZeroReg).addReg(PtrReg);
7316  BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7317  .addReg(TmpDestReg).addReg(MaskReg);
7318  BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7319  .addReg(TmpReg).addReg(OldVal3Reg);
7320  BuildMI(BB, dl, TII->get(PPC::BCC))
7321  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7322  BB->addSuccessor(loop2MBB);
7323  BB->addSuccessor(midMBB);
7324 
7325  BB = loop2MBB;
7326  BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7327  .addReg(TmpDestReg).addReg(MaskReg);
7328  BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7329  .addReg(Tmp2Reg).addReg(NewVal3Reg);
7330  BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7331  .addReg(ZeroReg).addReg(PtrReg);
7332  BuildMI(BB, dl, TII->get(PPC::BCC))
7333  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7334  BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7335  BB->addSuccessor(loop1MBB);
7336  BB->addSuccessor(exitMBB);
7337 
7338  BB = midMBB;
7339  BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7340  .addReg(ZeroReg).addReg(PtrReg);
7341  BB->addSuccessor(exitMBB);
7342 
7343  // exitMBB:
7344  // ...
7345  BB = exitMBB;
7346  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7347  .addReg(ShiftReg);
7348  } else if (MI->getOpcode() == PPC::FADDrtz) {
7349  // This pseudo performs an FADD with rounding mode temporarily forced
7350  // to round-to-zero. We emit this via custom inserter since the FPSCR
7351  // is not modeled at the SelectionDAG level.
7352  unsigned Dest = MI->getOperand(0).getReg();
7353  unsigned Src1 = MI->getOperand(1).getReg();
7354  unsigned Src2 = MI->getOperand(2).getReg();
7355  DebugLoc dl = MI->getDebugLoc();
7356 
7357  MachineRegisterInfo &RegInfo = F->getRegInfo();
7358  unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7359 
7360  // Save FPSCR value.
7361  BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7362 
7363  // Set rounding mode to round-to-zero.
7364  BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7365  BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7366 
7367  // Perform addition.
7368  BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7369 
7370  // Restore FPSCR value.
7371  BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7372  } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7373  MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7374  MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7375  MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7376  unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7377  MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7378  PPC::ANDIo8 : PPC::ANDIo;
7379  bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7380  MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7381 
7382  MachineRegisterInfo &RegInfo = F->getRegInfo();
7383  unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7384  &PPC::GPRCRegClass :
7385  &PPC::G8RCRegClass);
7386 
7387  DebugLoc dl = MI->getDebugLoc();
7388  BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7389  .addReg(MI->getOperand(1).getReg()).addImm(1);
7390  BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7391  MI->getOperand(0).getReg())
7392  .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7393  } else {
7394  llvm_unreachable("Unexpected instr type to insert");
7395  }
7396 
7397  MI->eraseFromParent(); // The pseudo instruction is gone now.
7398  return BB;
7399 }
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode) const
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
bool hasISEL() const
Definition: PPCSubtarget.h:211
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
F(f)
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:412
const HexagonInstrInfo * TII
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const MachineInstrBuilder & addImm(int64_t Val) const
MachineBasicBlock * EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, bool is64Bit, unsigned BinOpcode) const
const PPCSubtarget & Subtarget
int getOpcode() const
Definition: MachineInstr.h:270
int64_t getImm() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
static MachineOperand CreateImm(int64_t Val)
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
virtual Value* llvm::TargetLoweringBase::emitLoadLinked ( IRBuilder<> &  Builder,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtualinherited

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 932 of file TargetLowering.h.

933  {
934  llvm_unreachable("Load linked unimplemented on this target");
935  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineBasicBlock * PPCTargetLowering::EmitPartwordAtomicBinary ( MachineInstr MI,
MachineBasicBlock MBB,
bool  is8bit,
unsigned  Opcode 
) const

Definition at line 6584 of file PPCISelLowering.cpp.

6587  {
6588  // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6590  // In 64 bit mode we have to use 64 bits for addresses, even though the
6591  // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6592  // registers without caring whether they're 32 or 64, but here we're
6593  // doing actual arithmetic on the addresses.
6594  bool is64bit = Subtarget.isPPC64();
6595  unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6596 
6597  const BasicBlock *LLVM_BB = BB->getBasicBlock();
6598  MachineFunction *F = BB->getParent();
6599  MachineFunction::iterator It = BB;
6600  ++It;
6601 
6602  unsigned dest = MI->getOperand(0).getReg();
6603  unsigned ptrA = MI->getOperand(1).getReg();
6604  unsigned ptrB = MI->getOperand(2).getReg();
6605  unsigned incr = MI->getOperand(3).getReg();
6606  DebugLoc dl = MI->getDebugLoc();
6607 
6608  MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6609  MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6610  F->insert(It, loopMBB);
6611  F->insert(It, exitMBB);
6612  exitMBB->splice(exitMBB->begin(), BB,
6613  std::next(MachineBasicBlock::iterator(MI)), BB->end());
6614  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6615 
6616  MachineRegisterInfo &RegInfo = F->getRegInfo();
6617  const TargetRegisterClass *RC =
6618  is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6619  (const TargetRegisterClass *) &PPC::GPRCRegClass;
6620  unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6621  unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6622  unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6623  unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6624  unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6625  unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6626  unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6627  unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6628  unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6629  unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6630  unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6631  unsigned Ptr1Reg;
6632  unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6633 
6634  // thisMBB:
6635  // ...
6636  // fallthrough --> loopMBB
6637  BB->addSuccessor(loopMBB);
6638 
6639  // The 4-byte load must be aligned, while a char or short may be
6640  // anywhere in the word. Hence all this nasty bookkeeping code.
6641  // add ptr1, ptrA, ptrB [copy if ptrA==0]
6642  // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6643  // xori shift, shift1, 24 [16]
6644  // rlwinm ptr, ptr1, 0, 0, 29
6645  // slw incr2, incr, shift
6646  // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6647  // slw mask, mask2, shift
6648  // loopMBB:
6649  // lwarx tmpDest, ptr
6650  // add tmp, tmpDest, incr2
6651  // andc tmp2, tmpDest, mask
6652  // and tmp3, tmp, mask
6653  // or tmp4, tmp3, tmp2
6654  // stwcx. tmp4, ptr
6655  // bne- loopMBB
6656  // fallthrough --> exitMBB
6657  // srw dest, tmpDest, shift
6658  if (ptrA != ZeroReg) {
6659  Ptr1Reg = RegInfo.createVirtualRegister(RC);
6660  BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6661  .addReg(ptrA).addReg(ptrB);
6662  } else {
6663  Ptr1Reg = ptrB;
6664  }
6665  BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6666  .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6667  BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6668  .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6669  if (is64bit)
6670  BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6671  .addReg(Ptr1Reg).addImm(0).addImm(61);
6672  else
6673  BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6674  .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6675  BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6676  .addReg(incr).addReg(ShiftReg);
6677  if (is8bit)
6678  BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6679  else {
6680  BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6681  BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6682  }
6683  BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6684  .addReg(Mask2Reg).addReg(ShiftReg);
6685 
6686  BB = loopMBB;
6687  BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6688  .addReg(ZeroReg).addReg(PtrReg);
6689  if (BinOpcode)
6690  BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6691  .addReg(Incr2Reg).addReg(TmpDestReg);
6692  BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6693  .addReg(TmpDestReg).addReg(MaskReg);
6694  BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6695  .addReg(TmpReg).addReg(MaskReg);
6696  BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6697  .addReg(Tmp3Reg).addReg(Tmp2Reg);
6698  BuildMI(BB, dl, TII->get(PPC::STWCX))
6699  .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6700  BuildMI(BB, dl, TII->get(PPC::BCC))
6701  .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6702  BB->addSuccessor(loopMBB);
6703  BB->addSuccessor(exitMBB);
6704 
6705  // exitMBB:
6706  // ...
6707  BB = exitMBB;
6708  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6709  .addReg(ShiftReg);
6710  return BB;
6711 }
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
F(f)
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:412
const HexagonInstrInfo * TII
const MachineInstrBuilder & addImm(int64_t Val) const
const PPCSubtarget & Subtarget
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
virtual const TargetInstrInfo * getInstrInfo() const
bool isPPC64() const
Definition: PPCSubtarget.h:168
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
MachineRegisterInfo & getRegInfo()
unsigned getReg() const
getReg - Returns the register number.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr MI,
MachineBasicBlock MBB 
) const
protectedinherited

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 946 of file TargetLoweringBase.cpp.

947  {
948  MachineFunction &MF = *MI->getParent()->getParent();
949 
950  // MI changes inside this loop as we grow operands.
951  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
952  MachineOperand &MO = MI->getOperand(OperIdx);
953  if (!MO.isFI())
954  continue;
955 
956  // foldMemoryOperand builds a new MI after replacing a single FI operand
957  // with the canonical set of five x86 addressing-mode operands.
958  int FI = MO.getIndex();
959  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
960 
961  // Copy operands before the frame-index.
962  for (unsigned i = 0; i < OperIdx; ++i)
963  MIB.addOperand(MI->getOperand(i));
964  // Add frame index operands: direct-mem-ref tag, #FI, offset.
966  MIB.addOperand(MI->getOperand(OperIdx));
967  MIB.addImm(0);
968  // Copy the operands after the frame index.
969  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
970  MIB.addOperand(MI->getOperand(i));
971 
972  // Inherit previous memory operands.
973  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
974  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
975 
976  // Add a new memory operand for this FI.
977  const MachineFrameInfo &MFI = *MF.getFrameInfo();
978  assert(MFI.getObjectOffset(FI) != -1);
979  MachineMemOperand *MMO =
983  MFI.getObjectAlignment(FI));
984  MIB->addMemOperand(MF, MMO);
985 
986  // Replace the instruction and update the operand index.
987  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
988  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
989  MI->eraseFromParent();
990  MI = MIB;
991  }
992  return MBB;
993 }
The memory access reads data.
const MachineFunction * getParent() const
const TargetMachine & TM
True if this is a little endian target.
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:266
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
bool mayLoad(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:520
Abstract Stack Frame Information.
const MachineInstrBuilder & addImm(int64_t Val) const
unsigned getNumOperands() const
Definition: MachineInstr.h:274
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
assert(Globals.size() > 1)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
MachineFrameInfo * getFrameInfo()
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
virtual const DataLayout * getDataLayout() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.cpp:602
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
virtual Value* llvm::TargetLoweringBase::emitStoreConditional ( IRBuilder<> &  Builder,
Value Val,
Value Addr,
AtomicOrdering  Ord 
) const
inlinevirtualinherited

Perform a store-conditional operation to Addr. Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 939 of file TargetLowering.h.

940  {
941  llvm_unreachable("Store conditional unimplemented on this target");
942  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr ( SelectionDAG DAG,
int  SPDiff,
SDValue  Chain,
SDValue LROpOut,
SDValue FPOpOut,
bool  isDarwinABI,
SDLoc  dl 
) const
private

EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address stack slot. Returns the chain as result and the loaded frame pointers in LROpOut/FPOpout. Used when tail calling.

Definition at line 3426 of file PPCISelLowering.cpp.

3432  {
3433  if (SPDiff) {
3434  // Load the LR and FP stack slot for later adjusting.
3435  EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3436  LROpOut = getReturnAddrFrameIndex(DAG);
3437  LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3438  false, false, false, 0);
3439  Chain = SDValue(LROpOut.getNode(), 1);
3440 
3441  // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3442  // slot as the FP is never overwritten.
3443  if (isDarwinABI) {
3444  FPOpOut = getFramePointerFrameIndex(DAG);
3445  FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3446  false, false, false, 0);
3447  Chain = SDValue(FPOpOut.getNode(), 1);
3448  }
3449  }
3450  return Chain;
3451 }
const PPCSubtarget & Subtarget
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getReturnAddrFrameIndex(SelectionDAG &DAG) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getFramePointerFrameIndex(SelectionDAG &DAG) const
bool TargetLowering::expandFP_TO_SINT ( SDNode N,
SDValue Result,
SelectionDAG DAG 
) const
inherited

Expand float(f32) to SINT(i64) conversion

Parameters
NNode to expand
Resultoutput after conversion
Returns
True, if the expansion was successful, false otherwise

Definition at line 2889 of file TargetLowering.cpp.

2890  {
2891  EVT VT = Node->getOperand(0).getValueType();
2892  EVT NVT = Node->getValueType(0);
2893  SDLoc dl(SDValue(Node, 0));
2894 
2895  // FIXME: Only f32 to i64 conversions are supported.
2896  if (VT != MVT::f32 || NVT != MVT::i64)
2897  return false;
2898 
2899  // Expand f32 -> i64 conversion
2900  // This algorithm comes from compiler-rt's implementation of fixsfdi:
2901  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2902  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2903  VT.getSizeInBits());
2904  SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2905  SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2906  SDValue Bias = DAG.getConstant(127, IntVT);
2907  SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2908  IntVT);
2909  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2910  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2911 
2912  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2913 
2914  SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2915  DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2916  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2917  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2918 
2919  SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2920  DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2921  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2922  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2923 
2924  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2925  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2926  DAG.getConstant(0x00800000, IntVT));
2927 
2928  R = DAG.getZExtOrTrunc(R, dl, NVT);
2929 
2930 
2931  R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2932  DAG.getNode(ISD::SHL, dl, NVT, R,
2933  DAG.getZExtOrTrunc(
2934  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2935  dl, getShiftAmountTy(IntVT))),
2936  DAG.getNode(ISD::SRL, dl, NVT, R,
2937  DAG.getZExtOrTrunc(
2938  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2939  dl, getShiftAmountTy(IntVT))),
2940  ISD::SETGT);
2941 
2942  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2943  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2944  Sign);
2945 
2946  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2947  DAG.getConstant(0, NVT), Ret, ISD::SETLT);
2948  return true;
2949 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
EVT getShiftAmountTy(EVT LHSTy) const
const DomTreeNodeT * Node
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
virtual bool llvm::TargetLowering::ExpandInlineAsm ( CallInst ) const
inlinevirtualinherited

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2421 of file TargetLowering.h.

2421  {
2422  return false;
2423  }
bool TargetLowering::expandMUL ( SDNode N,
SDValue Lo,
SDValue Hi,
EVT  HiLoVT,
SelectionDAG DAG,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const
inherited

Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.

Parameters
HiLoVTThe value type to use for the Lo and Hi nodes.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded. false if it has not

Definition at line 2786 of file TargetLowering.cpp.

2788  {
2789  EVT VT = N->getValueType(0);
2790  SDLoc dl(N);
2791 
2792  bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2793  bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2794  bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2795  bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2796  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2797  unsigned OuterBitSize = VT.getSizeInBits();
2798  unsigned InnerBitSize = HiLoVT.getSizeInBits();
2799  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2800  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2801 
2802  // LL, LH, RL, and RH must be either all NULL or all set to a value.
2803  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2804  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2805 
2806  if (!LL.getNode() && !RL.getNode() &&
2808  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2809  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2810  }
2811 
2812  if (!LL.getNode())
2813  return false;
2814 
2815  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2816  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2817  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2818  // The inputs are both zero-extended.
2819  if (HasUMUL_LOHI) {
2820  // We can emit a umul_lohi.
2821  Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2822  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2823  Hi = SDValue(Lo.getNode(), 1);
2824  return true;
2825  }
2826  if (HasMULHU) {
2827  // We can emit a mulhu+mul.
2828  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2829  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2830  return true;
2831  }
2832  }
2833  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2834  // The input values are both sign-extended.
2835  if (HasSMUL_LOHI) {
2836  // We can emit a smul_lohi.
2837  Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2838  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2839  Hi = SDValue(Lo.getNode(), 1);
2840  return true;
2841  }
2842  if (HasMULHS) {
2843  // We can emit a mulhs+mul.
2844  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2845  Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2846  return true;
2847  }
2848  }
2849 
2850  if (!LH.getNode() && !RH.getNode() &&
2853  unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2854  SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2855  LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2856  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2857  RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2858  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2859  }
2860 
2861  if (!LH.getNode())
2862  return false;
2863 
2864  if (HasUMUL_LOHI) {
2865  // Lo,Hi = umul LHS, RHS.
2866  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2867  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2868  Lo = UMulLOHI;
2869  Hi = UMulLOHI.getValue(1);
2870  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2871  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2872  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2873  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2874  return true;
2875  }
2876  if (HasMULHU) {
2877  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2878  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2879  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2880  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2881  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2882  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2883  return true;
2884  }
2885  }
2886  return false;
2887 }
SDValue getValue(unsigned R) const
const SDValue & getOperand(unsigned Num) const
EVT getShiftAmountTy(EVT LHSTy) const
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Class for arbitrary precision integers.
Definition: APInt.h:75
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue PPCTargetLowering::extendArgForPPC64 ( ISD::ArgFlagsTy  Flags,
EVT  ObjectVT,
SelectionDAG DAG,
SDValue  ArgVal,
SDLoc  dl 
) const
private

Definition at line 2545 of file PPCISelLowering.cpp.

2547  {
2548  if (Flags.isSExt())
2549  ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2550  DAG.getValueType(ObjectVT));
2551  else if (Flags.isZExt())
2552  ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2553  DAG.getValueType(ObjectVT));
2554 
2555  return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2556 }
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getValueType(EVT)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
std::pair< const TargetRegisterClass *, uint8_t > TargetLoweringBase::findRepresentativeClass ( MVT  VT) const
protectedvirtualinherited

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 998 of file TargetLoweringBase.cpp.

998  {
1000  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1001  if (!RC)
1002  return std::make_pair(RC, 0);
1003 
1004  // Compute the set of all super-register classes.
1005  BitVector SuperRegRC(TRI->getNumRegClasses());
1006  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1007  SuperRegRC.setBitsInMask(RCI.getMask());
1008 
1009  // Find the first legal register class with the largest spill size.
1010  const TargetRegisterClass *BestRC = RC;
1011  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1012  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1013  // We want the largest possible spill size.
1014  if (SuperRC->getSize() <= BestRC->getSize())
1015  continue;
1016  if (!isLegalRC(SuperRC))
1017  continue;
1018  BestRC = SuperRC;
1019  }
1020  return std::make_pair(BestRC, 1);
1021 }
const TargetMachine & getTargetMachine() const
unsigned getNumRegClasses() const
const TargetRegisterClass * getRegClass(unsigned i) const
SimpleValueType SimpleTy
bool isLegalRC(const TargetRegisterClass *RC) const
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
virtual const TargetRegisterInfo * getRegisterInfo() const
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
Definition: BitVector.h:496
SDValue PPCTargetLowering::FinishCall ( CallingConv::ID  CallConv,
SDLoc  dl,
bool  isTailCall,
bool  isVarArg,
SelectionDAG DAG,
SmallVector< std::pair< unsigned, SDValue >, 8 > &  RegsToPass,
SDValue  InFlag,
SDValue  Chain,
SDValue Callee,
int  SPDiff,
unsigned  NumBytes,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 3767 of file PPCISelLowering.cpp.

3776  {
3777 
3778  bool isELFv2ABI = Subtarget.isELFv2ABI();
3779  std::vector<EVT> NodeTys;
3781  unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3782  isTailCall, RegsToPass, Ops, NodeTys,
3783  Subtarget);
3784 
3785  // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3786  if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3787  Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3788 
3789  // When performing tail call optimization the callee pops its arguments off
3790  // the stack. Account for this here so these bytes can be pushed back on in
3791  // PPCFrameLowering::eliminateCallFramePseudoInstr.
3792  int BytesCalleePops =
3795 
3796  // Add a register mask operand representing the call-preserved registers.
3798  const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3799  assert(Mask && "Missing call preserved mask for calling convention");
3800  Ops.push_back(DAG.getRegisterMask(Mask));
3801 
3802  if (InFlag.getNode())
3803  Ops.push_back(InFlag);
3804 
3805  // Emit tail call.
3806  if (isTailCall) {
3807  assert(((Callee.getOpcode() == ISD::Register &&
3808  cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3809  Callee.getOpcode() == ISD::TargetExternalSymbol ||
3810  Callee.getOpcode() == ISD::TargetGlobalAddress ||
3811  isa<ConstantSDNode>(Callee)) &&
3812  "Expecting an global address, external symbol, absolute value or register");
3813 
3814  return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3815  }
3816 
3817  // Add a NOP immediately after the branch instruction when using the 64-bit
3818  // SVR4 ABI. At link time, if caller and callee are in a different module and
3819  // thus have a different TOC, the call will be replaced with a call to a stub
3820  // function which saves the current TOC, loads the TOC of the callee and
3821  // branches to the callee. The NOP will be replaced with a load instruction
3822  // which restores the TOC of the caller from the TOC save slot of the current
3823  // stack frame. If caller and callee belong to the same module (and have the
3824  // same TOC), the NOP will remain unchanged.
3825 
3826  bool needsTOCRestore = false;
3827  if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3828  if (CallOpc == PPCISD::BCTRL) {
3829  // This is a call through a function pointer.
3830  // Restore the caller TOC from the save area into R2.
3831  // See PrepareCall() for more information about calls through function
3832  // pointers in the 64-bit SVR4 ABI.
3833  // We are using a target-specific load with r2 hard coded, because the
3834  // result of a target-independent load would never go directly into r2,
3835  // since r2 is a reserved register (which prevents the register allocator
3836  // from allocating it), resulting in an additional register being
3837  // allocated and an unnecessary move instruction being generated.
3838  needsTOCRestore = true;
3839  } else if ((CallOpc == PPCISD::CALL) &&
3840  (!isLocalCall(Callee) ||
3842  // Otherwise insert NOP for non-local calls.
3843  CallOpc = PPCISD::CALL_NOP;
3844  }
3845  }
3846 
3847  Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3848  InFlag = Chain.getValue(1);
3849 
3850  if (needsTOCRestore) {
3851  SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3852  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3853  SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3854  unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3855  SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3856  SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3857  Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3858  InFlag = Chain.getValue(1);
3859  }
3860 
3861  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3862  DAG.getIntPtrConstant(BytesCalleePops, true),
3863  InFlag, dl);
3864  if (!Ins.empty())
3865  InFlag = Chain.getValue(1);
3866 
3867  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3868  Ins, dl, DAG, InVals);
3869 }
SDValue getValue(unsigned R) const
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Definition: SelectionDAG.h:612
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
virtual const uint32_t * getCallPreservedMask(CallingConv::ID) const
static bool isLocalCall(const SDValue &Callee)
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
SDValue getRegisterMask(const uint32_t *RegMask)
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
unsigned getOpcode() const
unsigned GuaranteedTailCallOpt
bool isELFv2ABI() const
FIXME: Should use a command-line option.
Definition: PPCSubtarget.h:231
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
bool isPPC64() const
Definition: PPCSubtarget.h:168
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
virtual const TargetRegisterInfo * getRegisterInfo() const
static unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &Ops, std::vector< EVT > &NodeTys, const PPCSubtarget &Subtarget)
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
static unsigned getTOCSaveOffset(bool isELFv2ABI)
bool llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
inlineoverridevirtual

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv.

Reimplemented from llvm::TargetLowering.

Definition at line 516 of file PPCISelLowering.h.

517  {
518  // We support any array type as "consecutive" block in the parameter
519  // save area. The element type defines the alignment requirement and
520  // whether the argument should go in GPRs, FPRs, or VRs if available.
521  //
522  // Note that clang uses this capability both to implement the ELFv2
523  // homogeneous float/vector aggregate ABI, and to avoid having to use
524  // "byval" when passing aggregates that might fully fit in registers.
525  return Ty->isArrayTy();
526  }
virtual bool llvm::TargetLoweringBase::GetAddrModeArguments ( IntrinsicInst ,
SmallVectorImpl< Value * > &  ,
Type *&   
) const
inlinevirtualinherited

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Definition at line 1236 of file TargetLowering.h.

1238  {
1239  return false;
1240  }
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inlineinherited

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 290 of file TargetLowering.h.

290  {
291  if (isVec)
292  return BooleanVectorContents;
293  return isFloat ? BooleanFloatContents : BooleanContents;
294  }
BooleanContent BooleanVectorContents
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inlineinherited

Definition at line 296 of file TargetLowering.h.

296  {
297  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
298  }
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
RelocType Type
Definition: COFFYAML.cpp:285
const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inlineinherited

Returns map of slow types for division or remainder with corresponding fast types

Definition at line 222 of file TargetLowering.h.

222  {
223  return BypassSlowDivWidths;
224  }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
unsigned PPCTargetLowering::getByValTypeAlignment ( Type Ty) const
overridevirtual

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 746 of file PPCISelLowering.cpp.

746  {
747  // Darwin passes everything on 4 byte boundary.
748  if (Subtarget.isDarwin())
749  return 4;
750 
751  // 16byte and wider vectors are passed on 16byte boundary.
752  // The rest is 8 on PPC64 and 4 on PPC32 boundary.
753  unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755  getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
756  return Align;
757 }
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:221
bool hasAltivec() const
Definition: PPCSubtarget.h:207
bool hasQPX() const
Definition: PPCSubtarget.h:208
static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign, unsigned MaxMaxAlign)
const PPCSubtarget & Subtarget
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
bool isPPC64() const
Definition: PPCSubtarget.h:168
virtual const char* llvm::TargetLowering::getClearCacheBuiltinName ( ) const
inlinevirtualinherited

Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call

Reimplemented in llvm::X86TargetLowering.

Definition at line 2310 of file TargetLowering.h.

2310  {
2311  return "__clear_cache";
2312  }
ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inlineinherited

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 1437 of file TargetLowering.h.

1437  {
1438  return CmpLibcallCCs[Call];
1439  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtualinherited

Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Definition at line 1214 of file TargetLoweringBase.cpp.

1214  {
1215  return MVT::i32; // return the default value
1216 }
LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 589 of file TargetLowering.h.

589  {
590  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
591  ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
592  "Table isn't big enough!");
593  // See setCondCodeAction for how this is encoded.
594  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
595  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
596  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
597  assert(Action != Promote && "Can't promote condition code!");
598  return Action;
599  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
static int Value(bit_value_t V)
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
PPCTargetLowering::ConstraintType PPCTargetLowering::getConstraintType ( const std::string &  Constraint) const
overridevirtual

getConstraintType - Given a constraint, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 8805 of file PPCISelLowering.cpp.

8805  {
8806  if (Constraint.size() == 1) {
8807  switch (Constraint[0]) {
8808  default: break;
8809  case 'b':
8810  case 'r':
8811  case 'f':
8812  case 'v':
8813  case 'y':
8814  return C_RegisterClass;
8815  case 'Z':
8816  // FIXME: While Z does indicate a memory constraint, it specifically
8817  // indicates an r+r address (used in conjunction with the 'y' modifier
8818  // in the replacement string). Currently, we're forcing the base
8819  // register to be r0 in the asm printer (which is interpreted as zero)
8820  // and forming the complete address in the second register. This is
8821  // suboptimal.
8822  return C_Memory;
8823  }
8824  } else if (Constraint == "wc") { // individual CR bits.
8825  return C_RegisterClass;
8826  } else if (Constraint == "wa" || Constraint == "wd" ||
8827  Constraint == "wf" || Constraint == "ws") {
8828  return C_RegisterClass; // VSX registers.
8829  }
8830  return TargetLowering::getConstraintType(Constraint);
8831 }
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
const DataLayout* llvm::TargetLoweringBase::getDataLayout ( ) const
inlineinherited

Definition at line 150 of file TargetLowering.h.

150 { return DL; }
const DataLayout * DL
True if this is a little endian target.
unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception address on entry to a landing pad.

Definition at line 845 of file TargetLowering.h.

845  {
847  }
unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Definition at line 851 of file TargetLowering.h.

851  {
853  }
static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestaticinherited

Definition at line 124 of file TargetLowering.h.

124  {
125  switch (Content) {
127  // Extend by adding rubbish bits.
128  return ISD::ANY_EXTEND;
130  // Extend by adding zero bits.
131  return ISD::ZERO_EXTEND;
133  // Extend by copying the sign bit.
134  return ISD::SIGN_EXTEND;
135  }
136  llvm_unreachable("Invalid content kind");
137  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
SDValue PPCTargetLowering::getFramePointerFrameIndex ( SelectionDAG DAG) const
private

Definition at line 5133 of file PPCISelLowering.cpp.

5133  {
5134  MachineFunction &MF = DAG.getMachineFunction();
5135  bool isPPC64 = Subtarget.isPPC64();
5136  bool isDarwinABI = Subtarget.isDarwinABI();
5137  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5138 
5139  // Get current frame pointer save index. The users of this index will be
5140  // primarily DYNALLOC instructions.
5142  int FPSI = FI->getFramePointerSaveIndex();
5143 
5144  // If the frame pointer save index hasn't been defined yet.
5145  if (!FPSI) {
5146  // Find out what the fix offset of the frame pointer save area.
5147  int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5148  isDarwinABI);
5149 
5150  // Allocate the frame index for frame pointer save area.
5151  FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5152  // Save the result.
5153  FI->setFramePointerSaveIndex(FPSI);
5154  }
5155  return DAG.getFrameIndex(FPSI, PtrVT);
5156 }
bool isDarwinABI() const
Definition: PPCSubtarget.h:228
void setFramePointerSaveIndex(int Idx)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
const PPCSubtarget & Subtarget
static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI)
MachineFrameInfo * getFrameInfo()
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 553 of file TargetLowering.h.

553  {
555  "Table isn't big enough!");
556  unsigned Ty = (unsigned)VT.SimpleTy;
557  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
558  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 571 of file TargetLowering.h.

571  {
573  "Table isn't big enough!");
574  unsigned Ty = (unsigned)VT.SimpleTy;
575  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
576  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
assert(Globals.size() > 1)
bool llvm::TargetLoweringBase::getInsertFencesForAtomic ( ) const
inlineinherited

Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.

Definition at line 889 of file TargetLowering.h.

889  {
890  return InsertFencesForAtomic;
891  }
unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inlineinherited

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 863 of file TargetLowering.h.

863  {
864  return JumpBufAlignment;
865  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inlineinherited

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 857 of file TargetLowering.h.

857  {
858  return JumpBufSize;
859  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
unsigned TargetLowering::getJumpTableEncoding ( ) const
virtualinherited

Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented in llvm::MipsTargetLowering, llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::XCoreTargetLowering.

Definition at line 222 of file TargetLowering.cpp.

222  {
223  // In non-pic modes, just use the address of a block.
224  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
226 
227  // In PIC mode, if the target supports a GPRel32 directive, use it.
228  if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
230 
231  // Otherwise, use a label difference.
233 }
const TargetMachine & getTargetMachine() const
CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inlineinherited

Get the CallingConv that should be used for the specified libcall.

Definition at line 1447 of file TargetLowering.h.

1447  {
1448  return LibcallCallingConvs[Call];
1449  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inlineinherited

Get the libcall routine name for the specified libcall.

Definition at line 1425 of file TargetLowering.h.

1425  {
1426  return LibcallRoutineNames[Call];
1427  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
MVT  VT 
) const
inlineinherited

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 520 of file TargetLowering.h.

520  {
522  "Table isn't big enough!");
523  return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
524  }
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
virtual unsigned llvm::TargetLoweringBase::getMaximalGlobalOffset ( ) const
inlinevirtualinherited

Returns the maximal possible offset which can be used for loads / stores from the global.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 903 of file TargetLowering.h.

903  {
904  return 0;
905  }
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 758 of file TargetLowering.h.

758  {
760  }
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 768 of file TargetLowering.h.

768  {
770  }
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 748 of file TargetLowering.h.

748  {
750  }
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inlineinherited

Return the minimum function alignment.

Definition at line 873 of file TargetLowering.h.

873  {
874  return MinFunctionAlignment;
875  }
int llvm::TargetLoweringBase::getMinimumJumpTableEntries ( ) const
inlineinherited

Return integer threshold on number of blocks to use jump tables rather than if sequence.

Definition at line 833 of file TargetLowering.h.

833  {
835  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inlineinherited

Return the minimum stack alignment of an argument.

Definition at line 868 of file TargetLowering.h.

868  {
870  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight ( AsmOperandInfo info,
int  maIndex 
) const
virtualinherited

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2442 of file TargetLowering.cpp.

2443  {
2445  if (maIndex >= (int)info.multipleAlternatives.size())
2446  rCodes = &info.Codes;
2447  else
2448  rCodes = &info.multipleAlternatives[maIndex].Codes;
2449  ConstraintWeight BestWeight = CW_Invalid;
2450 
2451  // Loop over the options, keeping track of the most general one.
2452  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2453  ConstraintWeight weight =
2454  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2455  if (weight > BestWeight)
2456  BestWeight = weight;
2457  }
2458 
2459  return BestWeight;
2460 }
lazy value info
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:102
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 703 of file TargetLowering.h.

703  {
704  if (VT.isSimple()) {
705  assert((unsigned)VT.getSimpleVT().SimpleTy <
707  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
708  }
709  if (VT.isVector()) {
710  EVT VT1;
711  MVT VT2;
712  unsigned NumIntermediates;
713  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
714  }
715  if (VT.isInteger()) {
716  unsigned BitWidth = VT.getSizeInBits();
717  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
718  return (BitWidth + RegWidth - 1) / RegWidth;
719  }
720  llvm_unreachable("Unsupported extended type!");
721  }
unsigned getSizeInBits() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
const TargetLoweringObjectFile& llvm::TargetLoweringBase::getObjFileLowering ( ) const
inlineinherited

Definition at line 151 of file TargetLowering.h.

151 { return TLOF; }
const TargetLoweringObjectFile & TLOF
True if this is a little endian target.
LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 477 of file TargetLowering.h.

477  {
478  if (VT.isExtended()) return Expand;
479  // If a target-specific SDNode requires legalization, require the target
480  // to provide custom legalization for it.
481  if (Op > array_lengthof(OpActions[0])) return Custom;
482  unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
483  return (LegalizeAction)OpActions[I][Op];
484  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
#define I(x, y, z)
Definition: MD5.cpp:54
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
EVT PPCTargetLowering::getOptimalMemOpType ( uint64_t  Size,
unsigned  DstAlign,
unsigned  SrcAlign,
bool  IsMemset,
bool  ZeroMemset,
bool  MemcpyStrSrc,
MachineFunction MF 
) const
overridevirtual

getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9157 of file PPCISelLowering.cpp.

9161  {
9162  if (Subtarget.isPPC64()) {
9163  return MVT::i64;
9164  } else {
9165  return MVT::i32;
9166  }
9167 }
const PPCSubtarget & Subtarget
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG DAG 
) const
virtualinherited

Returns relocation base for the given PIC jumptable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 235 of file TargetLowering.cpp.

236  {
237  // If our PIC model is GP relative, use the global offset table as the base.
238  unsigned JTEncoding = getJumpTableEncoding();
239 
240  if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
242  return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
243 
244  return Table;
245 }
virtual MVT getPointerTy(uint32_t=0) const
virtual unsigned getJumpTableEncoding() const
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Definition: SelectionDAG.h:631
const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction MF,
unsigned  JTI,
MCContext Ctx 
) const
virtualinherited

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 251 of file TargetLowering.cpp.

252  {
253  // The normal PIC reloc base is the label at the start of the jump table.
254  return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
255 }
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:293
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
unsigned TargetLoweringBase::getPointerSizeInBits ( uint32_t  AS = 0) const
inherited

Definition at line 847 of file TargetLoweringBase.cpp.

847  {
848  return DL->getPointerSizeInBits(AS);
849 }
const DataLayout * DL
True if this is a little endian target.
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
MVT TargetLoweringBase::getPointerTy ( uint32_t  AS = 0) const
virtualinherited

Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Definition at line 843 of file TargetLoweringBase.cpp.

843  {
845 }
static MVT getIntegerVT(unsigned BitWidth)
unsigned getPointerSizeInBits(uint32_t AS=0) const
unsigned TargetLoweringBase::getPointerTypeSizeInBits ( Type Ty) const
inherited

Definition at line 851 of file TargetLoweringBase.cpp.

851  {
852  assert(Ty->isPointerTy());
854 }
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: Type.cpp:212
unsigned getPointerSizeInBits(uint32_t AS=0) const
assert(Globals.size() > 1)
bool isPointerTy() const
Definition: Type.h:217
virtual bool llvm::TargetLowering::getPostIndexedAddressParts ( SDNode ,
SDNode ,
SDValue ,
SDValue ,
ISD::MemIndexedMode ,
SelectionDAG  
) const
inlinevirtualinherited

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MSP430TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1881 of file TargetLowering.h.

1885  {
1886  return false;
1887  }
virtual TargetLoweringBase::LegalizeTypeAction llvm::TargetLoweringBase::getPreferredVectorAction ( EVT  VT) const
inlinevirtualinherited

Return the preferred vector type legalization action.

Reimplemented in llvm::X86TargetLowering, llvm::NVPTXTargetLowering, llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 190 of file TargetLowering.h.

190  {
191  // The default action for one element vectors is to scalarize
192  if (VT.getVectorNumElements() == 1)
193  return TypeScalarizeVector;
194  // The default action for other vectors is to promote
195  return TypePromoteInteger;
196  }
unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inlineinherited

Return the preferred function alignment.

Definition at line 878 of file TargetLowering.h.

878  {
879  return PrefFunctionAlignment;
880  }
unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( ) const
inlineinherited

Return the preferred loop alignment.

Definition at line 883 of file TargetLowering.h.

883  {
884  return PrefLoopAlignment;
885  }
unsigned PrefLoopAlignment
The preferred loop alignment.
bool PPCTargetLowering::getPreIndexedAddressParts ( SDNode N,
SDValue Base,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG 
) const
overridevirtual

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 1442 of file PPCISelLowering.cpp.

1445  {
1446  if (DisablePPCPreinc) return false;
1447 
1448  bool isLoad = true;
1449  SDValue Ptr;
1450  EVT VT;
1451  unsigned Alignment;
1452  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1453  Ptr = LD->getBasePtr();
1454  VT = LD->getMemoryVT();
1455  Alignment = LD->getAlignment();
1456  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1457  Ptr = ST->getBasePtr();
1458  VT = ST->getMemoryVT();
1459  Alignment = ST->getAlignment();
1460  isLoad = false;
1461  } else
1462  return false;
1463 
1464  // PowerPC doesn't have preinc load/store instructions for vectors.
1465  if (VT.isVector())
1466  return false;
1467 
1468  if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1469 
1470  // Common code will reject creating a pre-inc form if the base pointer
1471  // is a frame index, or if N is a store and the base pointer is either
1472  // the same as or a predecessor of the value being stored. Check for
1473  // those situations here, and try with swapped Base/Offset instead.
1474  bool Swap = false;
1475 
1476  if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1477  Swap = true;
1478  else if (!isLoad) {
1479  SDValue Val = cast<StoreSDNode>(N)->getValue();
1480  if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1481  Swap = true;
1482  }
1483 
1484  if (Swap)
1485  std::swap(Base, Offset);
1486 
1487  AM = ISD::PRE_INC;
1488  return true;
1489  }
1490 
1491  // LDU/STU can only handle immediates that are a multiple of 4.
1492  if (VT != MVT::i64) {
1493  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1494  return false;
1495  } else {
1496  // LDU/STU need an address with at least 4-byte alignment.
1497  if (Alignment < 4)
1498  return false;
1499 
1500  if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1501  return false;
1502  }
1503 
1504  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1505  // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1506  // sext i32 to i64 when addr mode is r+i.
1507  if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1508  LD->getExtensionType() == ISD::SEXTLOAD &&
1509  isa<ConstantSDNode>(Offset))
1510  return false;
1511  }
1512 
1513  AM = ISD::PRE_INC;
1514  return true;
1515 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
static cl::opt< bool > DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
SDNode * getNode() const
get the SDNode which holds the desired result
bool isPredecessorOf(const SDNode *N) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
#define N
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the register class that should be used for the specified value type.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 314 of file TargetLowering.h.

314  {
315  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
316  assert(RC && "This value type is not natively supported!");
317  return RC;
318  }
assert(Globals.size() > 1)
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
std::pair< unsigned, const TargetRegisterClass * > PPCTargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 8889 of file PPCISelLowering.cpp.

8890  {
8891  if (Constraint.size() == 1) {
8892  // GCC RS6000 Constraint Letters
8893  switch (Constraint[0]) {
8894  case 'b': // R1-R31
8895  if (VT == MVT::i64 && Subtarget.isPPC64())
8896  return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8897  return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8898  case 'r': // R0-R31
8899  if (VT == MVT::i64 && Subtarget.isPPC64())
8900  return std::make_pair(0U, &PPC::G8RCRegClass);
8901  return std::make_pair(0U, &PPC::GPRCRegClass);
8902  case 'f':
8903  if (VT == MVT::f32 || VT == MVT::i32)
8904  return std::make_pair(0U, &PPC::F4RCRegClass);
8905  if (VT == MVT::f64 || VT == MVT::i64)
8906  return std::make_pair(0U, &PPC::F8RCRegClass);
8907  break;
8908  case 'v':
8909  return std::make_pair(0U, &PPC::VRRCRegClass);
8910  case 'y': // crrc
8911  return std::make_pair(0U, &PPC::CRRCRegClass);
8912  }
8913  } else if (Constraint == "wc") { // an individual CR bit.
8914  return std::make_pair(0U, &PPC::CRBITRCRegClass);
8915  } else if (Constraint == "wa" || Constraint == "wd" ||
8916  Constraint == "wf") {
8917  return std::make_pair(0U, &PPC::VSRCRegClass);
8918  } else if (Constraint == "ws") {
8919  return std::make_pair(0U, &PPC::VSFRCRegClass);
8920  }
8921 
8922  std::pair<unsigned, const TargetRegisterClass*> R =
8924 
8925  // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8926  // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8927  // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8928  // register.
8929  // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8930  // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8931  if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8932  PPC::GPRCRegClass.contains(R.first)) {
8934  return std::make_pair(TRI->getMatchingSuperReg(R.first,
8935  PPC::sub_32, &PPC::G8RCRegClass),
8936  &PPC::G8RCRegClass);
8937  }
8938 
8939  return R;
8940 }
const TargetMachine & getTargetMachine() const
const PPCSubtarget & Subtarget
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
virtual const TargetRegisterInfo * getRegisterInfo() const
unsigned PPCTargetLowering::getRegisterByName ( const char *  RegName,
EVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 9118 of file PPCISelLowering.cpp.

9119  {
9120  bool isPPC64 = Subtarget.isPPC64();
9121  bool isDarwinABI = Subtarget.isDarwinABI();
9122 
9123  if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9124  (!isPPC64 && VT != MVT::i32))
9125  report_fatal_error("Invalid register global variable type");
9126 
9127  bool is64Bit = isPPC64 && VT == MVT::i64;
9128  unsigned Reg = StringSwitch<unsigned>(RegName)
9129  .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9130  .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9131  .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9132  (is64Bit ? PPC::X13 : PPC::R13))
9133  .Default(0);
9134 
9135  if (Reg)
9136  return Reg;
9137  report_fatal_error("Invalid register name global variable");
9138 }
bool isDarwinABI() const
Definition: PPCSubtarget.h:228
#define R2(n)
StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:55
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
static bool is64Bit(const ELFYAML::Object &Doc)
Definition: yaml2elf.cpp:463
Reg
All possible values of the reg field in the ModR/M byte.
const PPCSubtarget & Subtarget
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
R Default(const T &Value) const
Definition: StringSwitch.h:111
bool isPPC64() const
Definition: PPCSubtarget.h:168
MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 669 of file TargetLowering.h.

669  {
670  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
671  return RegisterTypeForVT[VT.SimpleTy];
672  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 675 of file TargetLowering.h.

675  {
676  if (VT.isSimple()) {
677  assert((unsigned)VT.getSimpleVT().SimpleTy <
679  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
680  }
681  if (VT.isVector()) {
682  EVT VT1;
683  MVT RegisterVT;
684  unsigned NumIntermediates;
685  (void)getVectorTypeBreakdown(Context, VT, VT1,
686  NumIntermediates, RegisterVT);
687  return RegisterVT;
688  }
689  if (VT.isInteger()) {
690  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
691  }
692  llvm_unreachable("Unsupported extended type!");
693  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtualinherited

Return the cost of the 'representative' register class for the specified value type.

Definition at line 334 of file TargetLowering.h.

334  {
335  return RepRegClassCostForVT[VT.SimpleTy];
336  }
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 327 of file TargetLowering.h.

327  {
328  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
329  return RC;
330  }
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
SDValue PPCTargetLowering::getReturnAddrFrameIndex ( SelectionDAG DAG) const
private

Definition at line 5109 of file PPCISelLowering.cpp.

5109  {
5110  MachineFunction &MF = DAG.getMachineFunction();
5111  bool isPPC64 = Subtarget.isPPC64();
5112  bool isDarwinABI = Subtarget.isDarwinABI();
5113  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5114 
5115  // Get current frame pointer save index. The users of this index will be
5116  // primarily DYNALLOC instructions.
5118  int RASI = FI->getReturnAddrSaveIndex();
5119 
5120  // If the frame pointer save index hasn't been defined yet.
5121  if (!RASI) {
5122  // Find out what the fix offset of the frame pointer save area.
5123  int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5124  // Allocate the frame index for frame pointer save area.
5125  RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5126  // Save the result.
5127  FI->setReturnAddrSaveIndex(RASI);
5128  }
5129  return DAG.getFrameIndex(RASI, PtrVT);
5130 }
bool isDarwinABI() const
Definition: PPCSubtarget.h:228
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
const PPCSubtarget & Subtarget
MachineFrameInfo * getFrameInfo()
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI)
MVT llvm::PPCTargetLowering::getScalarShiftAmountTy ( EVT  LHSTy) const
inlineoverridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 354 of file PPCISelLowering.h.

354 { return MVT::i32; }
virtual int llvm::TargetLoweringBase::getScalingFactorCost ( const AddrMode AM,
Type Ty 
) const
inlinevirtualinherited

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.

If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well.

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 1271 of file TargetLowering.h.

1271  {
1272  // Default: assume that any scaling factor used in a legal AM is free.
1273  if (isLegalAddressingMode(AM, Ty)) return 0;
1274  return -1;
1275  }
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inlineinherited

Return target scheduling preference.

Definition at line 301 of file TargetLowering.h.

301  {
302  return SchedPreferenceInfo;
303  }
Sched::Preference SchedPreferenceInfo
Sched::Preference PPCTargetLowering::getSchedulingPreference ( SDNode N) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9264 of file PPCISelLowering.cpp.

9264  {
9267 
9268  return Sched::ILP;
9269 }
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
const PPCSubtarget & Subtarget
bool enableMachineScheduler() const override
static cl::opt< bool > DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
virtual const MCPhysReg* llvm::TargetLowering::getScratchRegisters ( CallingConv::ID  CC) const
inlinevirtualinherited

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Reimplemented in llvm::X86TargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2344 of file TargetLowering.h.

2344  {
2345  return nullptr;
2346  }
EVT PPCTargetLowering::getSetCCResultType ( LLVMContext Context,
EVT  VT 
) const
overridevirtual

getSetCCResultType - Return the ISD::SETCC ValueType

Reimplemented from llvm::TargetLoweringBase.

Definition at line 824 of file PPCISelLowering.cpp.

824  {
825  if (!VT.isVector())
826  return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 }
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
const PPCSubtarget & Subtarget
bool useCRBits() const
Definition: PPCSubtarget.h:181
EVT changeVectorElementTypeToInteger() const
Definition: ValueTypes.h:81
EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy) const
inherited

Definition at line 860 of file TargetLoweringBase.cpp.

860  {
861  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
862  if (LHSTy.isVector())
863  return LHSTy;
864  return getScalarShiftAmountTy(LHSTy);
865 }
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
assert(Globals.size() > 1)
MVT llvm::TargetLoweringBase::getSimpleValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 659 of file TargetLowering.h.

659  {
660  return getValueType(Ty, AllowUnknown).getSimpleVT();
661  }
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
TargetLowering::ConstraintWeight PPCTargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo info,
const char *  constraint 
) const
overridevirtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 8837 of file PPCISelLowering.cpp.

8838  {
8839  ConstraintWeight weight = CW_Invalid;
8840  Value *CallOperandVal = info.CallOperandVal;
8841  // If we don't have a value, we can't do a match,
8842  // but allow it at the lowest weight.
8843  if (!CallOperandVal)
8844  return CW_Default;
8845  Type *type = CallOperandVal->getType();
8846 
8847  // Look at the constraint type.
8848  if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8849  return CW_Register; // an individual CR bit.
8850  else if ((StringRef(constraint) == "wa" ||
8851  StringRef(constraint) == "wd" ||
8852  StringRef(constraint) == "wf") &&
8853  type->isVectorTy())
8854  return CW_Register;
8855  else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8856  return CW_Register;
8857 
8858  switch (*constraint) {
8859  default:
8861  break;
8862  case 'b':
8863  if (type->isIntegerTy())
8864  weight = CW_Register;
8865  break;
8866  case 'f':
8867  if (type->isFloatTy())
8868  weight = CW_Register;
8869  break;
8870  case 'd':
8871  if (type->isDoubleTy())
8872  weight = CW_Register;
8873  break;
8874  case 'v':
8875  if (type->isVectorTy())
8876  weight = CW_Register;
8877  break;
8878  case 'y':
8879  weight = CW_Register;
8880  break;
8881  case 'Z':
8882  weight = CW_Memory;
8883  break;
8884  }
8885  return weight;
8886 }
bool isDoubleTy() const
isDoubleTy - Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:146
lazy value info
bool isVectorTy() const
Definition: Type.h:226
bool isFloatTy() const
isFloatTy - Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:143
Type * getType() const
Definition: Value.h:215
bool isIntegerTy() const
Definition: Type.h:193
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
virtual bool llvm::TargetLoweringBase::getStackCookieLocation ( unsigned &  ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented in llvm::X86TargetLowering.

Definition at line 896 of file TargetLowering.h.

897  {
898  return false;
899  }
unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inlineinherited

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 839 of file TargetLowering.h.

839  {
841  }
unsigned StackPointerRegisterToSaveRestore
const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inlineinherited

Definition at line 149 of file TargetLowering.h.

149 { return TM; }
const TargetMachine & TM
True if this is a little endian target.
const char * PPCTargetLowering::getTargetNodeName ( unsigned  Opcode) const
overridevirtual

getTargetNodeName() - This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 759 of file PPCISelLowering.cpp.

759  {
760  switch (Opcode) {
761  default: return nullptr;
762  case PPCISD::FSEL: return "PPCISD::FSEL";
763  case PPCISD::FCFID: return "PPCISD::FCFID";
764  case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
765  case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
766  case PPCISD::FRE: return "PPCISD::FRE";
767  case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
768  case PPCISD::STFIWX: return "PPCISD::STFIWX";
769  case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
770  case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
771  case PPCISD::VPERM: return "PPCISD::VPERM";
772  case PPCISD::Hi: return "PPCISD::Hi";
773  case PPCISD::Lo: return "PPCISD::Lo";
774  case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
775  case PPCISD::LOAD: return "PPCISD::LOAD";
776  case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
777  case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
778  case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
779  case PPCISD::SRL: return "PPCISD::SRL";
780  case PPCISD::SRA: return "PPCISD::SRA";
781  case PPCISD::SHL: return "PPCISD::SHL";
782  case PPCISD::CALL: return "PPCISD::CALL";
783  case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
784  case PPCISD::MTCTR: return "PPCISD::MTCTR";
785  case PPCISD::BCTRL: return "PPCISD::BCTRL";
786  case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
787  case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
788  case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
789  case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
790  case PPCISD::VCMP: return "PPCISD::VCMP";
791  case PPCISD::VCMPo: return "PPCISD::VCMPo";
792  case PPCISD::LBRX: return "PPCISD::LBRX";
793  case PPCISD::STBRX: return "PPCISD::STBRX";
794  case PPCISD::LARX: return "PPCISD::LARX";
795  case PPCISD::STCX: return "PPCISD::STCX";
796  case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
797  case PPCISD::BDNZ: return "PPCISD::BDNZ";
798  case PPCISD::BDZ: return "PPCISD::BDZ";
799  case PPCISD::MFFS: return "PPCISD::MFFS";
800  case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
801  case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
802  case PPCISD::CR6SET: return "PPCISD::CR6SET";
803  case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
804  case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
805  case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
806  case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
807  case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
808  case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
809  case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
810  case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
811  case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
812  case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
813  case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
814  case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
815  case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
816  case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
817  case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
818  case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
819  case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
820  case PPCISD::SC: return "PPCISD::SC";
821  }
822 }
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
Return with a flag operand, matched by 'blr'.
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Reciprocal estimate instructions (unary FP ops).
Like a regular LOAD but additionally taking/producing a flag.
virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic ( IntrinsicInfo ,
const CallInst ,
unsigned   
) const
inlinevirtualinherited

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 439 of file TargetLowering.h.

440  {
441  return false;
442  }
LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( MVT  ValVT,
MVT  MemVT 
) const
inlineinherited

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 535 of file TargetLowering.h.

535  {
536  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
537  "Table isn't big enough!");
538  return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
539  [MemVT.SimpleTy];
540  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
assert(Globals.size() > 1)
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 375 of file TargetLowering.h.

375  {
376  return getTypeConversion(Context, VT).first;
377  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inlineinherited

Definition at line 378 of file TargetLowering.h.

378  {
379  return ValueTypeActions.getTypeAction(VT);
380  }
LegalizeTypeAction getTypeAction(MVT VT) const
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind llvm::TargetLoweringBase::getTypeConversion ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

Reset the operation actions based on target options.

Definition at line 1629 of file TargetLowering.h.

1629  {
1630  // If this is a simple type, use the ComputeRegisterProp mechanism.
1631  if (VT.isSimple()) {
1632  MVT SVT = VT.getSimpleVT();
1633  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1634  MVT NVT = TransformToType[SVT.SimpleTy];
1636 
1637  assert(
1638  (LA == TypeLegal || LA == TypeSoftenFloat ||
1640  && "Promote may not follow Expand or Promote");
1641 
1642  if (LA == TypeSplitVector)
1643  return LegalizeKind(LA, EVT::getVectorVT(Context,
1644  SVT.getVectorElementType(),
1645  SVT.getVectorNumElements()/2));
1646  if (LA == TypeScalarizeVector)
1647  return LegalizeKind(LA, SVT.getVectorElementType());
1648  return LegalizeKind(LA, NVT);
1649  }
1650 
1651  // Handle Extended Scalar Types.
1652  if (!VT.isVector()) {
1653  assert(VT.isInteger() && "Float types must be simple");
1654  unsigned BitSize = VT.getSizeInBits();
1655  // First promote to a power-of-two size, then expand if necessary.
1656  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1657  EVT NVT = VT.getRoundIntegerType(Context);
1658  assert(NVT != VT && "Unable to round integer VT");
1659  LegalizeKind NextStep = getTypeConversion(Context, NVT);
1660  // Avoid multi-step promotion.
1661  if (NextStep.first == TypePromoteInteger) return NextStep;
1662  // Return rounded integer type.
1663  return LegalizeKind(TypePromoteInteger, NVT);
1664  }
1665 
1667  EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1668  }
1669 
1670  // Handle vector types.
1671  unsigned NumElts = VT.getVectorNumElements();
1672  EVT EltVT = VT.getVectorElementType();
1673 
1674  // Vectors with only one element are always scalarized.
1675  if (NumElts == 1)
1676  return LegalizeKind(TypeScalarizeVector, EltVT);
1677 
1678  // Try to widen vector elements until the element type is a power of two and
1679  // promote it to a legal type later on, for example:
1680  // <3 x i8> -> <4 x i8> -> <4 x i32>
1681  if (EltVT.isInteger()) {
1682  // Vectors with a number of elements that is not a power of two are always
1683  // widened, for example <3 x i8> -> <4 x i8>.
1684  if (!VT.isPow2VectorType()) {
1685  NumElts = (unsigned)NextPowerOf2(NumElts);
1686  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1687  return LegalizeKind(TypeWidenVector, NVT);
1688  }
1689 
1690  // Examine the element type.
1691  LegalizeKind LK = getTypeConversion(Context, EltVT);
1692 
1693  // If type is to be expanded, split the vector.
1694  // <4 x i140> -> <2 x i140>
1695  if (LK.first == TypeExpandInteger)
1697  EVT::getVectorVT(Context, EltVT, NumElts / 2));
1698 
1699  // Promote the integer element types until a legal vector type is found
1700  // or until the element integer type is too big. If a legal type was not
1701  // found, fallback to the usual mechanism of widening/splitting the
1702  // vector.
1703  EVT OldEltVT = EltVT;
1704  while (1) {
1705  // Increase the bitwidth of the element to the next pow-of-two
1706  // (which is greater than 8 bits).
1707  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1708  ).getRoundIntegerType(Context);
1709 
1710  // Stop trying when getting a non-simple element type.
1711  // Note that vector elements may be greater than legal vector element
1712  // types. Example: X86 XMM registers hold 64bit element on 32bit
1713  // systems.
1714  if (!EltVT.isSimple()) break;
1715 
1716  // Build a new vector type and check if it is legal.
1717  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1718  // Found a legal promoted vector type.
1719  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1721  EVT::getVectorVT(Context, EltVT, NumElts));
1722  }
1723 
1724  // Reset the type to the unexpanded type if we did not find a legal vector
1725  // type with a promoted vector element type.
1726  EltVT = OldEltVT;
1727  }
1728 
1729  // Try to widen the vector until a legal type is found.
1730  // If there is no wider legal type, split the vector.
1731  while (1) {
1732  // Round up to the next power of 2.
1733  NumElts = (unsigned)NextPowerOf2(NumElts);
1734 
1735  // If there is no simple vector type with this many elements then there
1736  // cannot be a larger legal vector type. Note that this assumes that
1737  // there are no skipped intermediate vector types in the simple types.
1738  if (!EltVT.isSimple()) break;
1739  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1740  if (LargerVector == MVT()) break;
1741 
1742  // If this type is legal then widen the vector.
1743  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1744  return LegalizeKind(TypeWidenVector, LargerVector);
1745  }
1746 
1747  // Widen odd vectors to next power of two.
1748  if (!VT.isPow2VectorType()) {
1749  EVT NVT = VT.getPow2VectorType(Context);
1750  return LegalizeKind(TypeWidenVector, NVT);
1751  }
1752 
1753  // Vectors with illegal element types are expanded.
1754  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1755  return LegalizeKind(TypeSplitVector, NVT);
1756  }
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT TransformToType[MVT::LAST_VALUETYPE]
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
LegalizeTypeAction getTypeAction(MVT VT) const
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
virtual MVT llvm::TargetLowering::getTypeForExtArgOrReturn ( MVT  VT,
ISD::NodeType   
) const
inlinevirtualinherited

Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. FIXME: Most C calling convention requires the return type to be promoted, but this is not true all the time, e.g. i1 on x86-64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2327 of file TargetLowering.h.

2328  {
2329  MVT MinVT = getRegisterType(MVT::i32);
2330  return VT.bitsLT(MinVT) ? MinVT : VT;
2331  }
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
std::pair< unsigned, MVT > TargetLoweringBase::getTypeLegalizationCost ( Type Ty) const
inherited

Estimate the cost of type-legalization and the legalized type.

Definition at line 1425 of file TargetLoweringBase.cpp.

1425  {
1426  LLVMContext &C = Ty->getContext();
1427  EVT MTy = getValueType(Ty);
1428 
1429  unsigned Cost = 1;
1430  // We keep legalizing the type until we find a legal kind. We assume that
1431  // the only operation that costs anything is the split. After splitting
1432  // we need to handle two types.
1433  while (true) {
1434  LegalizeKind LK = getTypeConversion(C, MTy);
1435 
1436  if (LK.first == TypeLegal)
1437  return std::make_pair(Cost, MTy.getSimpleVT());
1438 
1439  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1440  Cost *= 2;
1441 
1442  // Keep legalizing the type.
1443  MTy = LK.second;
1444  }
1445 }
std::pair< LegalizeTypeAction, EVT > LegalizeKind
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
MVT getSimpleVT() const
Definition: ValueTypes.h:204
EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 396 of file TargetLowering.h.

396  {
397  assert(!VT.isVector());
398  while (true) {
399  switch (getTypeAction(Context, VT)) {
400  case TypeLegal:
401  return VT;
402  case TypeExpandInteger:
403  VT = getTypeToTransformTo(Context, VT);
404  break;
405  default:
406  llvm_unreachable("Type is not legal nor is it to be expanded!");
407  }
408  }
409  }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
assert(Globals.size() > 1)
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inlineinherited

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 611 of file TargetLowering.h.

611  {
612  assert(getOperationAction(Op, VT) == Promote &&
613  "This operation isn't promoted!");
614 
615  // See if this has an explicit type specified.
616  std::map<std::pair<unsigned, MVT::SimpleValueType>,
617  MVT::SimpleValueType>::const_iterator PTTI =
618  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
619  if (PTTI != PromoteToType.end()) return PTTI->second;
620 
621  assert((VT.isInteger() || VT.isFloatingPoint()) &&
622  "Cannot autopromote this type, add it with AddPromotedToType.");
623 
624  MVT NVT = VT;
625  do {
626  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
627  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
628  "Didn't find type to promote to!");
629  } while (!isTypeLegal(NVT) ||
630  getOperationAction(Op, NVT) == Promote);
631  return NVT;
632  }
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 388 of file TargetLowering.h.

388  {
389  return getTypeConversion(Context, VT).second;
390  }
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
EVT llvm::TargetLoweringBase::getValueType ( Type Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 638 of file TargetLowering.h.

638  {
639  // Lower scalar pointers to native pointer types.
640  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
641  return getPointerTy(PTy->getAddressSpace());
642 
643  if (Ty->isVectorTy()) {
644  VectorType *VTy = cast<VectorType>(Ty);
645  Type *Elm = VTy->getElementType();
646  // Lower vectors of pointers to native pointer types.
647  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
648  EVT PointerTy(getPointerTy(PT->getAddressSpace()));
649  Elm = PointerTy.getTypeForEVT(Ty->getContext());
650  }
651 
652  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
653  VTy->getNumElements());
654  }
655  return EVT::getEVT(Ty, AllowUnknown);
656  }
void * PointerTy
Definition: GenericValue.h:23
virtual MVT getPointerTy(uint32_t=0) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
RelocType Type
Definition: COFFYAML.cpp:285
const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inlineinherited

Definition at line 367 of file TargetLowering.h.

367  {
368  return ValueTypeActions;
369  }
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( ) const
inlinevirtualinherited

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 169 of file TargetLowering.h.

169  {
170  return getPointerTy();
171  }
virtual MVT getPointerTy(uint32_t=0) const
unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext Context,
EVT  VT,
EVT IntermediateVT,
unsigned &  NumIntermediates,
MVT RegisterVT 
) const
inherited

Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1227 of file TargetLoweringBase.cpp.

1230  {
1231  unsigned NumElts = VT.getVectorNumElements();
1232 
1233  // If there is a wider vector type with the same element type as this one,
1234  // or a promoted vector type that has the same number of elements which
1235  // are wider, then we should convert to that legal vector type.
1236  // This handles things like <2 x float> -> <4 x float> and
1237  // <4 x i1> -> <4 x i32>.
1238  LegalizeTypeAction TA = getTypeAction(Context, VT);
1239  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1240  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1241  if (isTypeLegal(RegisterEVT)) {
1242  IntermediateVT = RegisterEVT;
1243  RegisterVT = RegisterEVT.getSimpleVT();
1244  NumIntermediates = 1;
1245  return 1;
1246  }
1247  }
1248 
1249  // Figure out the right, legal destination reg to copy into.
1250  EVT EltTy = VT.getVectorElementType();
1251 
1252  unsigned NumVectorRegs = 1;
1253 
1254  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1255  // could break down into LHS/RHS like LegalizeDAG does.
1256  if (!isPowerOf2_32(NumElts)) {
1257  NumVectorRegs = NumElts;
1258  NumElts = 1;
1259  }
1260 
1261  // Divide the input until we get to a supported size. This will always
1262  // end with a scalar if the target doesn't support vectors.
1263  while (NumElts > 1 && !isTypeLegal(
1264  EVT::getVectorVT(Context, EltTy, NumElts))) {
1265  NumElts >>= 1;
1266  NumVectorRegs <<= 1;
1267  }
1268 
1269  NumIntermediates = NumVectorRegs;
1270 
1271  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1272  if (!isTypeLegal(NewVT))
1273  NewVT = EltTy;
1274  IntermediateVT = NewVT;
1275 
1276  MVT DestVT = getRegisterType(Context, NewVT);
1277  RegisterVT = DestVT;
1278  unsigned NewVTSize = NewVT.getSizeInBits();
1279 
1280  // Convert sizes such as i33 to i64.
1281  if (!isPowerOf2_32(NewVTSize))
1282  NewVTSize = NextPowerOf2(NewVTSize);
1283 
1284  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1285  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1286 
1287  // Otherwise, promotion or legal types use the same number of registers as
1288  // the vector decimated to the appropriate level.
1289  return NumVectorRegs;
1290 }
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
unsigned getSizeInBits() const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
bool isTypeLegal(EVT VT) const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
MVT getSimpleVT() const
Definition: ValueTypes.h:204
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
virtual void llvm::TargetLowering::HandleByVal ( CCState ,
unsigned &  ,
unsigned   
) const
inlinevirtualinherited

Target-specific cleanup for formal ByVal parameters.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2266 of file TargetLowering.h.

2266 {}
bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT) const
inlineinherited

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 731 of file TargetLowering.h.

731  {
732  return isBigEndian() || VT == MVT::ppcf128;
733  }
bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inlineinherited

Return true if the target has BitExtract instructions.

Definition at line 186 of file TargetLowering.h.

bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inlineinherited

Return true if multiple condition registers are available.

Definition at line 181 of file TargetLowering.h.

181  {
183  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( Type ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1356 of file TargetLowering.h.

1357  {
1358  return false;
1359  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
unsigned &   
) const
inlinevirtualinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1361 of file TargetLowering.h.

1362  {
1363  return false;
1364  }
bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inlineinherited

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 737 of file TargetLowering.h.

737  {
738  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
739  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
740  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void TargetLoweringBase::initActions ( )
protectedinherited

Initialize all of the actions to default values.

Definition at line 733 of file TargetLoweringBase.cpp.

733  {
734  // All operations default to being supported.
735  memset(OpActions, 0, sizeof(OpActions));
736  memset(LoadExtActions, 0, sizeof(LoadExtActions));
742 
743  // Set default actions for various operations.
744  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
745  // Default all indexed load / store to expand.
746  for (unsigned IM = (unsigned)ISD::PRE_INC;
747  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
750  }
751 
752  // Most backends expect to see the node which just returns the value loaded.
755 
756  // These operations default to expand.
759 
760  // These library functions default to expand.
762 
763  // These operations default to expand for vector types.
764  if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
773  }
774  }
775 
776  // Most targets ignore the @llvm.prefetch intrinsic.
778 
779  // ConstantFP nodes default to expand. Targets can either change this to
780  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
781  // to optimize expansions for certain constants.
787 
788  // These library functions default to expand.
833 
834  // Default ISD::TRAP to expand (which turns it into abort).
836 
837  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
838  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
839  //
841 }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:625
void *memset(void *b, int c, size_t len);
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const
inherited

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1353 of file TargetLoweringBase.cpp.

1353  {
1354  enum InstructionOpcodes {
1355 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1356 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1357 #include "llvm/IR/Instruction.def"
1358  };
1359  switch (static_cast<InstructionOpcodes>(Opcode)) {
1360  case Ret: return 0;
1361  case Br: return 0;
1362  case Switch: return 0;
1363  case IndirectBr: return 0;
1364  case Invoke: return 0;
1365  case Resume: return 0;
1366  case Unreachable: return 0;
1367  case Add: return ISD::ADD;
1368  case FAdd: return ISD::FADD;
1369  case Sub: return ISD::SUB;
1370  case FSub: return ISD::FSUB;
1371  case Mul: return ISD::MUL;
1372  case FMul: return ISD::FMUL;
1373  case UDiv: return ISD::UDIV;
1374  case SDiv: return ISD::SDIV;
1375  case FDiv: return ISD::FDIV;
1376  case URem: return ISD::UREM;
1377  case SRem: return ISD::SREM;
1378  case FRem: return ISD::FREM;
1379  case Shl: return ISD::SHL;
1380  case LShr: return ISD::SRL;
1381  case AShr: return ISD::SRA;
1382  case And: return ISD::AND;
1383  case Or: return ISD::OR;
1384  case Xor: return ISD::XOR;
1385  case Alloca: return 0;
1386  case Load: return ISD::LOAD;
1387  case Store: return ISD::STORE;
1388  case GetElementPtr: return 0;
1389  case Fence: return 0;
1390  case AtomicCmpXchg: return 0;
1391  case AtomicRMW: return 0;
1392  case Trunc: return ISD::TRUNCATE;
1393  case ZExt: return ISD::ZERO_EXTEND;
1394  case SExt: return ISD::SIGN_EXTEND;
1395  case FPToUI: return ISD::FP_TO_UINT;
1396  case FPToSI: return ISD::FP_TO_SINT;
1397  case UIToFP: return ISD::UINT_TO_FP;
1398  case SIToFP: return ISD::SINT_TO_FP;
1399  case FPTrunc: return ISD::FP_ROUND;
1400  case FPExt: return ISD::FP_EXTEND;
1401  case PtrToInt: return ISD::BITCAST;
1402  case IntToPtr: return ISD::BITCAST;
1403  case BitCast: return ISD::BITCAST;
1404  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1405  case ICmp: return ISD::SETCC;
1406  case FCmp: return ISD::SETCC;
1407  case PHI: return 0;
1408  case Call: return 0;
1409  case Select: return ISD::SELECT;
1410  case UserOp1: return 0;
1411  case UserOp2: return 0;
1412  case VAArg: return 0;
1414  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1415  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1416  case ExtractValue: return ISD::MERGE_VALUES;
1417  case InsertValue: return ISD::MERGE_VALUES;
1418  case LandingPad: return 0;
1419  }
1420 
1421  llvm_unreachable("Unknown instruction type encountered!");
1422 }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1875
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool llvm::TargetLoweringBase::isBigEndian ( ) const
inlineinherited

Definition at line 153 of file TargetLowering.h.

153 { return !IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return true if the specified condition code is legal on this target.

Definition at line 602 of file TargetLowering.h.

602  {
603  return
604  getCondCodeAction(CC, VT) == Legal ||
605  getCondCodeAction(CC, VT) == Custom;
606  }
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
bool TargetLowering::isConstFalseVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Definition at line 1179 of file TargetLowering.cpp.

1179  {
1180  if (!N)
1181  return false;
1182 
1183  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1184  if (!CN) {
1186  if (!BV)
1187  return false;
1188 
1189  BitVector UndefElements;
1190  CN = BV->getConstantSplatNode(&UndefElements);
1191  // Only interested in constant splats, and we don't try to handle undef
1192  // elements in identifying boolean constants.
1193  if (!CN || UndefElements.none())
1194  return false;
1195  }
1196 
1198  return !CN->getAPIntValue()[0];
1199 
1200  return CN->isNullValue();
1201 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool TargetLowering::isConstTrueVal ( const SDNode N) const
inherited

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Definition at line 1149 of file TargetLowering.cpp.

1149  {
1150  if (!N)
1151  return false;
1152 
1153  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1154  if (!CN) {
1156  if (!BV)
1157  return false;
1158 
1159  BitVector UndefElements;
1160  CN = BV->getConstantSplatNode(&UndefElements);
1161  // Only interested in constant splats, and we don't try to handle undef
1162  // elements in identifying boolean constants.
1163  if (!CN || UndefElements.none())
1164  return false;
1165  }
1166 
1167  switch (getBooleanContents(N->getValueType(0))) {
1169  return CN->getAPIntValue()[0];
1171  return CN->isOne();
1173  return CN->isAllOnesValue();
1174  }
1175 
1176  llvm_unreachable("Invalid boolean contents");
1177 }
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
bool isAllOnesValue() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
const APInt & getAPIntValue() const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift ( const SDNode N) const
inlinevirtualinherited

Return true if it is profitable to move a following shift through this.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2060 of file TargetLowering.h.

2060  {
2061  return true;
2062  }
virtual bool llvm::TargetLowering::IsDesirableToPromoteOp ( SDValue  ,
EVT  
) const
inlinevirtualinherited

This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2084 of file TargetLowering.h.

2084  {
2085  return false;
2086  }
virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp ( unsigned  ,
EVT   
) const
inlinevirtualinherited

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2076 of file TargetLowering.h.

2077  {
2078  return false;
2079  }
bool PPCTargetLowering::IsEligibleForTailCallOptimization ( SDValue  Callee,
CallingConv::ID  CalleeCC,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SelectionDAG DAG 
) const
private

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.

Definition at line 3285 of file PPCISelLowering.cpp.

3289  {
3290  if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3291  return false;
3292 
3293  // Variable argument functions are not supported.
3294  if (isVarArg)
3295  return false;
3296 
3297  MachineFunction &MF = DAG.getMachineFunction();
3298  CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3299  if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3300  // Functions containing by val parameters are not supported.
3301  for (unsigned i = 0; i != Ins.size(); i++) {
3302  ISD::ArgFlagsTy Flags = Ins[i].Flags;
3303  if (Flags.isByVal()) return false;
3304  }
3305 
3306  // Non-PIC/GOT tail calls are supported.
3308  return true;
3309 
3310  // At the moment we can only do local tail calls (in same module, hidden
3311  // or protected) if we are generating PIC.
3312  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3313  return G->getGlobal()->hasHiddenVisibility()
3314  || G->getGlobal()->hasProtectedVisibility();
3315  }
3316 
3317  return false;
3318 }
Reloc::Model getRelocationModel() const
const TargetMachine & getTargetMachine() const
const Function * getFunction() const
CallingConv::ID getCallingConv() const
Definition: Function.h:161
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
#define G(x, y, z)
Definition: MD5.cpp:52
std::string Options
Definition: llvm-ar.cpp:73
virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1382 of file TargetLowering.h.

1382  {
1383  assert(VT.isFloatingPoint());
1384  return false;
1385  }
assert(Globals.size() > 1)
bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd ( EVT  VT) const
overridevirtual

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9238 of file PPCISelLowering.cpp.

9238  {
9239  VT = VT.getScalarType();
9240 
9241  if (!VT.isSimple())
9242  return false;
9243 
9244  switch (VT.getSimpleVT().SimpleTy) {
9245  case MVT::f32:
9246  case MVT::f64:
9247  return true;
9248  default:
9249  break;
9250  }
9251 
9252  return false;
9253 }
SimpleValueType SimpleTy
EVT getScalarType() const
Definition: ValueTypes.h:211
bool isSimple() const
Definition: ValueTypes.h:95
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1375 of file TargetLowering.h.

1375  {
1376  assert(VT.isFloatingPoint());
1377  return false;
1378  }
assert(Globals.size() > 1)
virtual bool llvm::TargetLoweringBase::isFPImmLegal ( const APFloat ,
EVT   
) const
inlinevirtualinherited

Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented in llvm::X86TargetLowering, llvm::MipsTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::HexagonTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 447 of file TargetLowering.h.

447  {
448  return false;
449  }
bool TargetLowering::isGAPlusOffset ( SDNode N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
virtualinherited

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2005 of file TargetLowering.cpp.

2006  {
2007  if (isa<GlobalAddressSDNode>(N)) {
2008  GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2009  GA = GASD->getGlobal();
2010  Offset += GASD->getOffset();
2011  return true;
2012  }
2013 
2014  if (N->getOpcode() == ISD::ADD) {
2015  SDValue N1 = N->getOperand(0);
2016  SDValue N2 = N->getOperand(1);
2017  if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2019  if (V) {
2020  Offset += V->getSExtValue();
2021  return true;
2022  }
2023  } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2025  if (V) {
2026  Offset += V->getSExtValue();
2027  return true;
2028  }
2029  }
2030  }
2031 
2032  return false;
2033 }
const GlobalValue * getGlobal() const
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
int64_t getSExtValue() const
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
#define N
bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 561 of file TargetLowering.h.

561  {
562  return VT.isSimple() &&
563  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
564  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
565  }
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 579 of file TargetLowering.h.

579  {
580  return VT.isSimple() &&
581  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
582  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
583  }
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
bool TargetLowering::isInTailCallPosition ( SelectionDAG DAG,
SDNode Node,
SDValue Chain 
) const
inherited

Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.

Definition at line 48 of file TargetLowering.cpp.

49  {
50  const Function *F = DAG.getMachineFunction().getFunction();
51 
52  // Conservatively require the attributes of the call to match those of
53  // the return. Ignore noalias because it doesn't affect the call sequence.
54  AttributeSet CallerAttrs = F->getAttributes();
55  if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56  .removeAttribute(Attribute::NoAlias).hasAttributes())
57  return false;
58 
59  // It's not safe to eliminate the sign / zero extension of the return value.
62  return false;
63 
64  // Check if the only use is a function return node.
65  return isUsedByReturnOnly(Node, Chain);
66 }
Sign extended before/after call.
Definition: Attributes.h:101
F(f)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Considered to not alias after call.
Definition: Attributes.h:82
Zero extended before/after call.
Definition: Attributes.h:114
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
bool llvm::TargetLoweringBase::isIntDivCheap ( ) const
inlineinherited

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 215 of file TargetLowering.h.

215 { return IntDivIsCheap; }
bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inlineinherited

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 231 of file TargetLowering.h.

231 { return JumpIsExpensive; }
bool PPCTargetLowering::isLegalAddImmediate ( int64_t  Imm) const
overridevirtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9201 of file PPCISelLowering.cpp.

9201  {
9202  return isInt<16>(Imm) || isUInt<16>(Imm);
9203 }
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:281
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:307
bool PPCTargetLowering::isLegalAddressingMode ( const AddrMode AM,
Type Ty 
) const
overridevirtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9015 of file PPCISelLowering.cpp.

9016  {
9017  // FIXME: PPC does not allow r+i addressing modes for vectors!
9018 
9019  // PPC allows a sign-extended 16-bit immediate field.
9020  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9021  return false;
9022 
9023  // No global is ever allowed as a base.
9024  if (AM.BaseGV)
9025  return false;
9026 
9027  // PPC only support r+r,
9028  switch (AM.Scale) {
9029  case 0: // "r+i" or just "i", depending on HasBaseReg.
9030  break;
9031  case 1:
9032  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9033  return false;
9034  // Otherwise we have r+r or r+i.
9035  break;
9036  case 2:
9037  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9038  return false;
9039  // Allow 2*r as r+r.
9040  break;
9041  default:
9042  // No other scales are supported.
9043  return false;
9044  }
9045 
9046  return true;
9047 }
bool PPCTargetLowering::isLegalICmpImmediate ( int64_t  Imm) const
overridevirtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9197 of file PPCISelLowering.cpp.

9197  {
9198  return isInt<16>(Imm) || isUInt<16>(Imm);
9199 }
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:281
bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:307
bool TargetLoweringBase::isLegalRC ( const TargetRegisterClass RC) const
protectedinherited

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 934 of file TargetLoweringBase.cpp.

934  {
935  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
936  I != E; ++I) {
937  if (isTypeLegal(*I))
938  return true;
939  }
940  return false;
941 }
vt_iterator vt_end() const
bool isTypeLegal(EVT VT) const
#define I(x, y, z)
Definition: MD5.cpp:54
vt_iterator vt_begin() const
bool llvm::TargetLoweringBase::isLittleEndian ( ) const
inlineinherited

Definition at line 154 of file TargetLowering.h.

154 { return IsLittleEndian; }
bool IsLittleEndian
True if this is a little endian target.
virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  ,
EVT   
) const
inlinevirtualinherited

isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 246 of file TargetLowering.h.

246  {
247  return true;
248  }
bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  VT 
) const
inlineinherited

Return true if the specified load with extension is legal on this target.

Definition at line 527 of file TargetLowering.h.

527  {
528  return VT.isSimple() &&
529  getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
530  }
LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const
bool llvm::TargetLoweringBase::isMaskAndBranchFoldingLegal ( ) const
inlineinherited

Return if the target supports combining a chain like:

%andResult = and %val1, #imm-with-one-bit-set;
%icmpResult = icmp %andResult, 0
br i1 %icmpResult, label %dest1, label %dest2

into a single machine instruction of a form like:

brOnBitSet %register, #bitNumber, dest

Definition at line 261 of file TargetLowering.h.

261  {
263  }
virtual bool llvm::TargetLoweringBase::isNarrowingProfitable ( EVT  ,
EVT   
) const
inlinevirtualinherited

Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented in llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1402 of file TargetLowering.h.

1402  {
1403  return false;
1404  }
virtual bool llvm::TargetLoweringBase::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
inlinevirtualinherited

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 908 of file TargetLowering.h.

908  {
909  return false;
910  }
bool PPCTargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode GA) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 9141 of file PPCISelLowering.cpp.

9141  {
9142  // The PowerPC target isn't yet aware of offsets.
9143  return false;
9144 }
bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 507 of file TargetLowering.h.

507  {
508  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
509  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target.

Definition at line 512 of file TargetLowering.h.

512  {
513  return (VT == MVT::Other || isTypeLegal(VT)) &&
514  getOperationAction(Op, VT) == Legal;
515  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 489 of file TargetLowering.h.

489  {
490  return (VT == MVT::Other || isTypeLegal(VT)) &&
491  (getOperationAction(Op, VT) == Legal ||
492  getOperationAction(Op, VT) == Custom);
493  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.

Definition at line 498 of file TargetLowering.h.

498  {
499  return (VT == MVT::Other || isTypeLegal(VT)) &&
500  (getOperationAction(Op, VT) == Legal ||
501  getOperationAction(Op, VT) == Promote);
502  }
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isPow2DivCheap ( ) const
inlineinherited

Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 227 of file TargetLowering.h.

227 { return Pow2DivIsCheap; }
bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inlineinherited

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 235 of file TargetLowering.h.

235  {
237  }
virtual bool llvm::TargetLoweringBase::isSafeMemOpType ( MVT  ) const
inlinevirtualinherited

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented in llvm::X86TargetLowering.

Definition at line 814 of file TargetLowering.h.

814 { return true; }
bool llvm::TargetLoweringBase::isSelectExpensive ( ) const
inlineinherited

Return true if the select operation is expensive for this target.

Definition at line 174 of file TargetLowering.h.

174 { return SelectIsExpensive; }
virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtualinherited

Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 176 of file TargetLowering.h.

176  {
177  return true;
178  }
virtual bool llvm::TargetLoweringBase::isShuffleMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtualinherited

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::MipsSETargetLowering.

Definition at line 455 of file TargetLowering.h.

456  {
457  return true;
458  }
bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inlineinherited

Returns true if target has indicated at least one type should be bypassed.

Definition at line 218 of file TargetLowering.h.

218 { return !BypassSlowDivWidths.empty(); }
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: DenseMap.h:68
bool PPCTargetLowering::isTruncateFree ( Type Ty1,
Type Ty2 
) const
overridevirtual

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in register X1 to i32 by referencing its sub-register R1.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9181 of file PPCISelLowering.cpp.

9181  {
9182  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9183  return false;
9184  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9185  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9186  return NumBits1 == 64 && NumBits2 == 32;
9187 }
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool PPCTargetLowering::isTruncateFree ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9189 of file PPCISelLowering.cpp.

9189  {
9190  if (!VT1.isInteger() || !VT2.isInteger())
9191  return false;
9192  unsigned NumBits1 = VT1.getSizeInBits();
9193  unsigned NumBits2 = VT2.getSizeInBits();
9194  return NumBits1 == 64 && NumBits2 == 32;
9195 }
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inlineinherited

Return true if the specified store with truncation is legal on this target.

Definition at line 544 of file TargetLowering.h.

544  {
545  return isTypeLegal(ValVT) && MemVT.isSimple() &&
546  getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
547  }
LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const
bool isTypeLegal(EVT VT) const
virtual bool llvm::TargetLowering::isTypeDesirableForOp ( unsigned  ,
EVT  VT 
) const
inlinevirtualinherited

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2068 of file TargetLowering.h.

2068  {
2069  // By default, assume all legal types are desirable.
2070  return isTypeLegal(VT);
2071  }
bool isTypeLegal(EVT VT) const
bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inlineinherited

Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Definition at line 341 of file TargetLowering.h.

341  {
342  assert(!VT.isSimple() ||
343  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
344  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
345  }
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
virtual bool llvm::TargetLowering::isUsedByReturnOnly ( SDNode ,
SDValue  
) const
inlinevirtualinherited

Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call.

This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 2297 of file TargetLowering.h.

2297  {
2298  return false;
2299  }
virtual bool llvm::TargetLoweringBase::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  ,
EVT   
) const
inlinevirtualinherited

Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented in llvm::X86TargetLowering.

Definition at line 469 of file TargetLowering.h.

470  {
471  return false;
472  }
virtual bool llvm::TargetLoweringBase::isVectorShiftByScalarCheap ( Type Ty) const
inlinevirtualinherited

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1295 of file TargetLowering.h.

1295  {
1296  return false;
1297  }
virtual bool llvm::TargetLoweringBase::isZExtFree ( Type ,
Type  
) const
inlinevirtualinherited

Return true if any actual instruction that defines a value of type Ty1 implicitly zero-extends the value to Ty2 in the result register.

This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1327 of file TargetLowering.h.

1327  {
1328  return false;
1329  }
virtual bool llvm::TargetLoweringBase::isZExtFree ( EVT  ,
EVT   
) const
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 1331 of file TargetLowering.h.

1331  {
1332  return false;
1333  }
virtual bool llvm::TargetLoweringBase::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
inlinevirtualinherited

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::MSP430TargetLowering, llvm::AMDGPUTargetLowering, and llvm::XCoreTargetLowering.

Definition at line 1369 of file TargetLowering.h.

1369  {
1370  return isZExtFree(Val.getValueType(), VT2);
1371  }
virtual bool isZExtFree(Type *, Type *) const
SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1962 of file PPCISelLowering.cpp.

1963  {
1964  return Op.getOperand(0);
1965 }
const SDValue & getOperand(unsigned i) const
void PPCTargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG DAG 
) const
overridevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 8945 of file PPCISelLowering.cpp.

8948  {
8949  SDValue Result;
8950 
8951  // Only support length 1 constraints.
8952  if (Constraint.length() > 1) return;
8953 
8954  char Letter = Constraint[0];
8955  switch (Letter) {
8956  default: break;
8957  case 'I':
8958  case 'J':
8959  case 'K':
8960  case 'L':
8961  case 'M':
8962  case 'N':
8963  case 'O':
8964  case 'P': {
8966  if (!CST) return; // Must be an immediate to match.
8967  unsigned Value = CST->getZExtValue();
8968  switch (Letter) {
8969  default: llvm_unreachable("Unknown constraint letter!");
8970  case 'I': // "I" is a signed 16-bit constant.
8971  if ((short)Value == (int)Value)
8972  Result = DAG.getTargetConstant(Value, Op.getValueType());
8973  break;
8974  case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8975  case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8976  if ((short)Value == 0)
8977  Result = DAG.getTargetConstant(Value, Op.getValueType());
8978  break;
8979  case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8980  if ((Value >> 16) == 0)
8981  Result = DAG.getTargetConstant(Value, Op.getValueType());
8982  break;
8983  case 'M': // "M" is a constant that is greater than 31.
8984  if (Value > 31)
8985  Result = DAG.getTargetConstant(Value, Op.getValueType());
8986  break;
8987  case 'N': // "N" is a positive constant that is an exact power of two.
8988  if ((int)Value > 0 && isPowerOf2_32(Value))
8989  Result = DAG.getTargetConstant(Value, Op.getValueType());
8990  break;
8991  case 'O': // "O" is the constant zero.
8992  if (Value == 0)
8993  Result = DAG.getTargetConstant(Value, Op.getValueType());
8994  break;
8995  case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8996  if ((short)-Value == (int)-Value)
8997  Result = DAG.getTargetConstant(Value, Op.getValueType());
8998  break;
8999  }
9000  break;
9001  }
9002  }
9003 
9004  if (Result.getNode()) {
9005  Ops.push_back(Result);
9006  return;
9007  }
9008 
9009  // Handle standard constraint letters.
9010  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9011 }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
EVT getValueType() const
LLVM Value Representation.
Definition: Value.h:69
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
uint64_t getZExtValue() const
SDValue PPCTargetLowering::LowerBlockAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1631 of file PPCISelLowering.cpp.

1632  {
1633  EVT PtrVT = Op.getValueType();
1634 
1635  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1636 
1637  unsigned MOHiFlag, MOLoFlag;
1638  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1639  SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1640  SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1641  return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1642 }
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:480
EVT getValueType() const
SDValue PPCTargetLowering::LowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5772 of file PPCISelLowering.cpp.

5773  {
5774  SDLoc dl(Op);
5776  assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5777 
5778  // Check if this is a splat of a constant value.
5779  APInt APSplatBits, APSplatUndef;
5780  unsigned SplatBitSize;
5781  bool HasAnyUndefs;
5782  if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5783  HasAnyUndefs, 0, true) || SplatBitSize > 32)
5784  return SDValue();
5785 
5786  unsigned SplatBits = APSplatBits.getZExtValue();
5787  unsigned SplatUndef = APSplatUndef.getZExtValue();
5788  unsigned SplatSize = SplatBitSize / 8;
5789 
5790  // First, handle single instruction cases.
5791 
5792  // All zeros?
5793  if (SplatBits == 0) {
5794  // Canonicalize all zero vectors to be v4i32.
5795  if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5796  SDValue Z = DAG.getConstant(0, MVT::i32);
5797  Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5798  Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5799  }
5800  return Op;
5801  }
5802 
5803  // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5804  int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5805  (32-SplatBitSize));
5806  if (SextVal >= -16 && SextVal <= 15)
5807  return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5808 
5809 
5810  // Two instruction sequences.
5811 
5812  // If this value is in the range [-32,30] and is even, use:
5813  // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5814  // If this value is in the range [17,31] and is odd, use:
5815  // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5816  // If this value is in the range [-31,-17] and is odd, use:
5817  // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5818  // Note the last two are three-instruction sequences.
5819  if (SextVal >= -32 && SextVal <= 31) {
5820  // To avoid having these optimizations undone by constant folding,
5821  // we convert to a pseudo that will be expanded later into one of
5822  // the above forms.
5823  SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5824  EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5825  (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5826  SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5827  SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5828  if (VT == Op.getValueType())
5829  return RetVal;
5830  else
5831  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5832  }
5833 
5834  // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5835  // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5836  // for fneg/fabs.
5837  if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5838  // Make -1 and vspltisw -1:
5839  SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5840 
5841  // Make the VSLW intrinsic, computing 0x8000_0000.
5842  SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5843  OnesV, DAG, dl);
5844 
5845  // xor by OnesV to invert it.
5846  Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5847  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5848  }
5849 
5850  // The remaining cases assume either big endian element order or
5851  // a splat-size that equates to the element size of the vector
5852  // to be built. An example that doesn't work for little endian is
5853  // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5854  // and a vector element size of 16 bits. The code below will
5855  // produce the vector in big endian element order, which for little
5856  // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5857 
5858  // For now, just avoid these optimizations in that case.
5859  // FIXME: Develop correct optimizations for LE with mismatched
5860  // splat and element sizes.
5861 
5862  if (Subtarget.isLittleEndian() &&
5863  SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5864  return SDValue();
5865 
5866  // Check to see if this is a wide variety of vsplti*, binop self cases.
5867  static const signed char SplatCsts[] = {
5868  -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5869  -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5870  };
5871 
5872  for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5873  // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5874  // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5875  int i = SplatCsts[idx];
5876 
5877  // Figure out what shift amount will be used by altivec if shifted by i in
5878  // this splat size.
5879  unsigned TypeShiftAmt = i & (SplatBitSize-1);
5880 
5881  // vsplti + shl self.
5882  if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5883  SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5884  static const unsigned IIDs[] = { // Intrinsic to use for each size.
5885  Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5886  Intrinsic::ppc_altivec_vslw
5887  };
5888  Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5889  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5890  }
5891 
5892  // vsplti + srl self.
5893  if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5894  SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5895  static const unsigned IIDs[] = { // Intrinsic to use for each size.
5896  Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5897  Intrinsic::ppc_altivec_vsrw
5898  };
5899  Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5900  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5901  }
5902 
5903  // vsplti + sra self.
5904  if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5905  SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5906  static const unsigned IIDs[] = { // Intrinsic to use for each size.
5907  Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5908  Intrinsic::ppc_altivec_vsraw
5909  };
5910  Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5911  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5912  }
5913 
5914  // vsplti + rol self.
5915  if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5916  ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5917  SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5918  static const unsigned IIDs[] = { // Intrinsic to use for each size.
5919  Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5920  Intrinsic::ppc_altivec_vrlw
5921  };
5922  Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5923  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5924  }
5925 
5926  // t = vsplti c, result = vsldoi t, t, 1
5927  if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5928  SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5929  return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5930  }
5931  // t = vsplti c, result = vsldoi t, t, 2
5932  if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5933  SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5934  return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5935  }
5936  // t = vsplti c, result = vsldoi t, t, 3
5937  if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5938  SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5939  return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5940  }
5941  }
5942 
5943  return SDValue();
5944 }
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, SDLoc dl)
EVT getVectorElementType() const
Definition: ValueTypes.h:217
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
const PPCSubtarget & Subtarget
#define T
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, SDLoc dl)
Class for arbitrary precision integers.
Definition: APInt.h:75
static RegisterPass< SwOnly > Z("legup-sw-only","Replace accelerated functions with wrappers and produce legup_wrappers")
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue PPCTargetLowering::LowerCall ( TargetLowering::CallLoweringInfo CLI,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 3872 of file PPCISelLowering.cpp.

3873  {
3874  SelectionDAG &DAG = CLI.DAG;
3875  SDLoc &dl = CLI.DL;
3877  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3879  SDValue Chain = CLI.Chain;
3880  SDValue Callee = CLI.Callee;
3881  bool &isTailCall = CLI.IsTailCall;
3883  bool isVarArg = CLI.IsVarArg;
3884 
3885  if (isTailCall)
3886  isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3887  Ins, DAG);
3888 
3889  if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3890  report_fatal_error("failed to perform tail call elimination on a call "
3891  "site marked musttail");
3892 
3893  if (Subtarget.isSVR4ABI()) {
3894  if (Subtarget.isPPC64())
3895  return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3896  isTailCall, Outs, OutVals, Ins,
3897  dl, DAG, InVals);
3898  else
3899  return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3900  isTailCall, Outs, OutVals, Ins,
3901  dl, DAG, InVals);
3902  }
3903 
3904  return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3905  isTailCall, Outs, OutVals, Ins,
3906  dl, DAG, InVals);
3907 }
SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
SmallVector< ISD::InputArg, 32 > Ins
const PPCSubtarget & Subtarget
SmallVector< ISD::OutputArg, 32 > Outs
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
SmallVector< SDValue, 32 > OutVals
SDValue PPCTargetLowering::LowerCall_32SVR4 ( SDValue  Chain,
SDValue  Callee,
CallingConv::ID  CallConv,
bool  isVarArg,
bool  isTailCall,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 3910 of file PPCISelLowering.cpp.

3917  {
3918  // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3919  // of the 32-bit SVR4 ABI stack frame layout.
3920 
3922  CallConv == CallingConv::Fast) && "Unknown calling convention!");
3923 
3924  unsigned PtrByteSize = 4;
3925 
3926  MachineFunction &MF = DAG.getMachineFunction();
3927 
3928  // Mark this function as potentially containing a function that contains a
3929  // tail call. As a consequence the frame pointer will be used for dynamicalloc
3930  // and restoring the callers stack pointer in this functions epilog. This is
3931  // done because by tail calling the called function might overwrite the value
3932  // in this function's (MF) stack pointer stack slot 0(SP).
3933  if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3935  MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3936 
3937  // Count how many bytes are to be pushed on the stack, including the linkage
3938  // area, parameter list area and the part of the local variable space which
3939  // contains copies of aggregates which are passed by value.
3940 
3941  // Assign locations to all of the outgoing arguments.
3943  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3944  getTargetMachine(), ArgLocs, *DAG.getContext());
3945 
3946  // Reserve space for the linkage area on the stack.
3947  CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3948  PtrByteSize);
3949 
3950  if (isVarArg) {
3951  // Handle fixed and variable vector arguments differently.
3952  // Fixed vector arguments go into registers as long as registers are
3953  // available. Variable vector arguments always go into memory.
3954  unsigned NumArgs = Outs.size();
3955 
3956  for (unsigned i = 0; i != NumArgs; ++i) {
3957  MVT ArgVT = Outs[i].VT;
3958  ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3959  bool Result;
3960 
3961  if (Outs[i].IsFixed) {
3962  Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3963  CCInfo);
3964  } else {
3965  Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3966  ArgFlags, CCInfo);
3967  }
3968 
3969  if (Result) {
3970 #ifndef NDEBUG
3971  errs() << "Call operand #" << i << " has unhandled type "
3972  << EVT(ArgVT).getEVTString() << "\n";
3973 #endif
3974  llvm_unreachable(nullptr);
3975  }
3976  }
3977  } else {
3978  // All arguments are treated the same.
3979  CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3980  }
3981 
3982  // Assign locations to all of the outgoing aggregate by value arguments.
3983  SmallVector<CCValAssign, 16> ByValArgLocs;
3984  CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3985  getTargetMachine(), ByValArgLocs, *DAG.getContext());
3986 
3987  // Reserve stack space for the allocations in CCInfo.
3988  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3989 
3990  CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3991 
3992  // Size of the linkage area, parameter list area and the part of the local
3993  // space variable where copies of aggregates which are passed by value are
3994  // stored.
3995  unsigned NumBytes = CCByValInfo.getNextStackOffset();
3996 
3997  // Calculate by how many bytes the stack has to be adjusted in case of tail
3998  // call optimization.
3999  int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4000 
4001  // Adjust the stack pointer for the new arguments...
4002  // These operations are automatically eliminated by the prolog/epilog pass
4003  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4004  dl);
4005  SDValue CallSeqStart = Chain;
4006 
4007  // Load the return address and frame pointer so it can be moved somewhere else
4008  // later.
4009  SDValue LROp, FPOp;
4010  Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4011  dl);
4012 
4013  // Set up a copy of the stack pointer for use loading and storing any
4014  // arguments that may not fit in the registers available for argument
4015  // passing.
4016  SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4017 
4019  SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4020  SmallVector<SDValue, 8> MemOpChains;
4021 
4022  bool seenFloatArg = false;
4023  // Walk the register/memloc assignments, inserting copies/loads.
4024  for (unsigned i = 0, j = 0, e = ArgLocs.size();
4025  i != e;
4026  ++i) {
4027  CCValAssign &VA = ArgLocs[i];
4028  SDValue Arg = OutVals[i];
4029  ISD::ArgFlagsTy Flags = Outs[i].Flags;
4030 
4031  if (Flags.isByVal()) {
4032  // Argument is an aggregate which is passed by value, thus we need to
4033  // create a copy of it in the local variable space of the current stack
4034  // frame (which is the stack frame of the caller) and pass the address of
4035  // this copy to the callee.
4036  assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4037  CCValAssign &ByValVA = ByValArgLocs[j++];
4038  assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4039 
4040  // Memory reserved in the local variable space of the callers stack frame.
4041  unsigned LocMemOffset = ByValVA.getLocMemOffset();
4042 
4043  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4044  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4045 
4046  // Create a copy of the argument in the local area of the current
4047  // stack frame.
4048  SDValue MemcpyCall =
4049  CreateCopyOfByValArgument(Arg, PtrOff,
4050  CallSeqStart.getNode()->getOperand(0),
4051  Flags, DAG, dl);
4052 
4053  // This must go outside the CALLSEQ_START..END.
4054  SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4055  CallSeqStart.getNode()->getOperand(1),
4056  SDLoc(MemcpyCall));
4057  DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4058  NewCallSeqStart.getNode());
4059  Chain = CallSeqStart = NewCallSeqStart;
4060 
4061  // Pass the address of the aggregate copy on the stack either in a
4062  // physical register or in the parameter list area of the current stack
4063  // frame to the callee.
4064  Arg = PtrOff;
4065  }
4066 
4067  if (VA.isRegLoc()) {
4068  if (Arg.getValueType() == MVT::i1)
4069  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4070 
4071  seenFloatArg |= VA.getLocVT().isFloatingPoint();
4072  // Put argument in a physical register.
4073  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4074  } else {
4075  // Put argument in the parameter list area of the current stack frame.
4076  assert(VA.isMemLoc());
4077  unsigned LocMemOffset = VA.getLocMemOffset();
4078 
4079  if (!isTailCall) {
4080  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4081  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4082 
4083  MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4085  false, false, 0));
4086  } else {
4087  // Calculate and remember argument location.
4088  CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4089  TailCallArguments);
4090  }
4091  }
4092  }
4093 
4094  if (!MemOpChains.empty())
4095  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4096 
4097  // Build a sequence of copy-to-reg nodes chained together with token chain
4098  // and flag operands which copy the outgoing args into the appropriate regs.
4099  SDValue InFlag;
4100  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4101  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4102  RegsToPass[i].second, InFlag);
4103  InFlag = Chain.getValue(1);
4104  }
4105 
4106  // Set CR bit 6 to true if this is a vararg call with floating args passed in
4107  // registers.
4108  if (isVarArg) {
4109  SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4110  SDValue Ops[] = { Chain, InFlag };
4111 
4112  Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4113  dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4114 
4115  InFlag = Chain.getValue(1);
4116  }
4117 
4118  if (isTailCall)
4119  PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4120  false, TailCallArguments);
4121 
4122  return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4123  RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4124  Ins, InVals);
4125 }
SDValue getValue(unsigned R) const
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
raw_ostream & errs()
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
static void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
const SDValue & getOperand(unsigned Num) const
unsigned getValNo() const
bool isRegLoc() const
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:106
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:276
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
unsigned getLocReg() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< SDValue > &InVals) const
MVT getLocVT() const
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
static void CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
bool isMemLoc() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, SDLoc dl) const
SDValue getRegister(unsigned Reg, EVT VT)
unsigned getLocMemOffset() const
std::string Options
Definition: llvm-ar.cpp:73
unsigned AllocateStack(unsigned Size, unsigned Align)
SDValue PPCTargetLowering::LowerCall_64SVR4 ( SDValue  Chain,
SDValue  Callee,
CallingConv::ID  CallConv,
bool  isVarArg,
bool  isTailCall,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 4148 of file PPCISelLowering.cpp.

4155  {
4156 
4157  bool isELFv2ABI = Subtarget.isELFv2ABI();
4159  unsigned NumOps = Outs.size();
4160 
4161  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4162  unsigned PtrByteSize = 8;
4163 
4164  MachineFunction &MF = DAG.getMachineFunction();
4165 
4166  // Mark this function as potentially containing a function that contains a
4167  // tail call. As a consequence the frame pointer will be used for dynamicalloc
4168  // and restoring the callers stack pointer in this functions epilog. This is
4169  // done because by tail calling the called function might overwrite the value
4170  // in this function's (MF) stack pointer stack slot 0(SP).
4171  if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4173  MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4174 
4175  // Count how many bytes are to be pushed on the stack, including the linkage
4176  // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4177  // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4178  // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4179  unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4180  isELFv2ABI);
4181  unsigned NumBytes = LinkageSize;
4182 
4183  // Add up all the space actually used.
4184  for (unsigned i = 0; i != NumOps; ++i) {
4185  ISD::ArgFlagsTy Flags = Outs[i].Flags;
4186  EVT ArgVT = Outs[i].VT;
4187  EVT OrigVT = Outs[i].ArgVT;
4188 
4189  /* Respect alignment of argument on the stack. */
4190  unsigned Align =
4191  CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4192  NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4193 
4194  NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4195  if (Flags.isInConsecutiveRegsLast())
4196  NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4197  }
4198 
4199  unsigned NumBytesActuallyUsed = NumBytes;
4200 
4201  // The prolog code of the callee may store up to 8 GPR argument registers to
4202  // the stack, allowing va_start to index over them in memory if its varargs.
4203  // Because we cannot tell if this is needed on the caller side, we have to
4204  // conservatively assume that it is needed. As such, make sure we have at
4205  // least enough stack space for the caller to store the 8 GPRs.
4206  // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4207  NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4208 
4209  // Tail call needs the stack to be aligned.
4210  if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4212  NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4213 
4214  // Calculate by how many bytes the stack has to be adjusted in case of tail
4215  // call optimization.
4216  int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4217 
4218  // To protect arguments on the stack from being clobbered in a tail call,
4219  // force all the loads to happen before doing any other lowering.
4220  if (isTailCall)
4221  Chain = DAG.getStackArgumentTokenFactor(Chain);
4222 
4223  // Adjust the stack pointer for the new arguments...
4224  // These operations are automatically eliminated by the prolog/epilog pass
4225  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4226  dl);
4227  SDValue CallSeqStart = Chain;
4228 
4229  // Load the return address and frame pointer so it can be move somewhere else
4230  // later.
4231  SDValue LROp, FPOp;
4232  Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4233  dl);
4234 
4235  // Set up a copy of the stack pointer for use loading and storing any
4236  // arguments that may not fit in the registers available for argument
4237  // passing.
4238  SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4239 
4240  // Figure out which arguments are going to go in registers, and which in
4241  // memory. Also, if this is a vararg function, floating point operations
4242  // must be stored to our stack, and loaded into integer regs as well, if
4243  // any integer regs are available for argument passing.
4244  unsigned ArgOffset = LinkageSize;
4245  unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4246 
4247  static const MCPhysReg GPR[] = {
4248  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4249  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4250  };
4251  static const MCPhysReg *FPR = GetFPR();
4252 
4253  static const MCPhysReg VR[] = {
4254  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4255  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4256  };
4257  static const MCPhysReg VSRH[] = {
4258  PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4259  PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4260  };
4261 
4262  const unsigned NumGPRs = array_lengthof(GPR);
4263  const unsigned NumFPRs = 13;
4264  const unsigned NumVRs = array_lengthof(VR);
4265 
4267  SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4268 
4269  SmallVector<SDValue, 8> MemOpChains;
4270  for (unsigned i = 0; i != NumOps; ++i) {
4271  SDValue Arg = OutVals[i];
4272  ISD::ArgFlagsTy Flags = Outs[i].Flags;
4273  EVT ArgVT = Outs[i].VT;
4274  EVT OrigVT = Outs[i].ArgVT;
4275 
4276  /* Respect alignment of argument on the stack. */
4277  unsigned Align =
4278  CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4279  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4280 
4281  /* Compute GPR index associated with argument offset. */
4282  GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4283  GPR_idx = std::min(GPR_idx, NumGPRs);
4284 
4285  // PtrOff will be used to store the current argument to the stack if a
4286  // register cannot be found for it.
4287  SDValue PtrOff;
4288 
4289  PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4290 
4291  PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4292 
4293  // Promote integers to 64-bit values.
4294  if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4295  // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4296  unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4297  Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4298  }
4299 
4300  // FIXME memcpy is used way more than necessary. Correctness first.
4301  // Note: "by value" is code for passing a structure by value, not
4302  // basic types.
4303  if (Flags.isByVal()) {
4304  // Note: Size includes alignment padding, so
4305  // struct x { short a; char b; }
4306  // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4307  // These are the proper values we need for right-justifying the
4308  // aggregate in a parameter register.
4309  unsigned Size = Flags.getByValSize();
4310 
4311  // An empty aggregate parameter takes up no storage and no
4312  // registers.
4313  if (Size == 0)
4314  continue;
4315 
4316  // All aggregates smaller than 8 bytes must be passed right-justified.
4317  if (Size==1 || Size==2 || Size==4) {
4318  EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4319  if (GPR_idx != NumGPRs) {
4320  SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4321  MachinePointerInfo(), VT,
4322  false, false, 0);
4323  MemOpChains.push_back(Load.getValue(1));
4324  RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4325 
4326  ArgOffset += PtrByteSize;
4327  continue;
4328  }
4329  }
4330 
4331  if (GPR_idx == NumGPRs && Size < 8) {
4332  SDValue AddPtr = PtrOff;
4333  if (!isLittleEndian) {
4334  SDValue Const = DAG.getConstant(PtrByteSize - Size,
4335  PtrOff.getValueType());
4336  AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4337  }
4338  Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4339  CallSeqStart,
4340  Flags, DAG, dl);
4341  ArgOffset += PtrByteSize;
4342  continue;
4343  }
4344  // Copy entire object into memory. There are cases where gcc-generated
4345  // code assumes it is there, even if it could be put entirely into
4346  // registers. (This is not what the doc says.)
4347 
4348  // FIXME: The above statement is likely due to a misunderstanding of the
4349  // documents. All arguments must be copied into the parameter area BY
4350  // THE CALLEE in the event that the callee takes the address of any
4351  // formal argument. That has not yet been implemented. However, it is
4352  // reasonable to use the stack area as a staging area for the register
4353  // load.
4354 
4355  // Skip this for small aggregates, as we will use the same slot for a
4356  // right-justified copy, below.
4357  if (Size >= 8)
4358  Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4359  CallSeqStart,
4360  Flags, DAG, dl);
4361 
4362  // When a register is available, pass a small aggregate right-justified.
4363  if (Size < 8 && GPR_idx != NumGPRs) {
4364  // The easiest way to get this right-justified in a register
4365  // is to copy the structure into the rightmost portion of a
4366  // local variable slot, then load the whole slot into the
4367  // register.
4368  // FIXME: The memcpy seems to produce pretty awful code for
4369  // small aggregates, particularly for packed ones.
4370  // FIXME: It would be preferable to use the slot in the
4371  // parameter save area instead of a new local variable.
4372  SDValue AddPtr = PtrOff;
4373  if (!isLittleEndian) {
4374  SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4375  AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4376  }
4377  Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4378  CallSeqStart,
4379  Flags, DAG, dl);
4380 
4381  // Load the slot into the register.
4382  SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4384  false, false, false, 0);
4385  MemOpChains.push_back(Load.getValue(1));
4386  RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4387 
4388  // Done with this argument.
4389  ArgOffset += PtrByteSize;
4390  continue;
4391  }
4392 
4393  // For aggregates larger than PtrByteSize, copy the pieces of the
4394  // object that fit into registers from the parameter save area.
4395  for (unsigned j=0; j<Size; j+=PtrByteSize) {
4396  SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4397  SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4398  if (GPR_idx != NumGPRs) {
4399  SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4401  false, false, false, 0);
4402  MemOpChains.push_back(Load.getValue(1));
4403  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4404  ArgOffset += PtrByteSize;
4405  } else {
4406  ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4407  break;
4408  }
4409  }
4410  continue;
4411  }
4412 
4413  switch (Arg.getSimpleValueType().SimpleTy) {
4414  default: llvm_unreachable("Unexpected ValueType for argument!");
4415  case MVT::i1:
4416  case MVT::i32:
4417  case MVT::i64:
4418  // These can be scalar arguments or elements of an integer array type
4419  // passed directly. Clang may use those instead of "byval" aggregate
4420  // types to avoid forcing arguments to memory unnecessarily.
4421  if (GPR_idx != NumGPRs) {
4422  RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4423  } else {
4424  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4425  true, isTailCall, false, MemOpChains,
4426  TailCallArguments, dl);
4427  }
4428  ArgOffset += PtrByteSize;
4429  break;
4430  case MVT::f32:
4431  case MVT::f64: {
4432  // These can be scalar arguments or elements of a float array type
4433  // passed directly. The latter are used to implement ELFv2 homogenous
4434  // float aggregates.
4435 
4436  // Named arguments go into FPRs first, and once they overflow, the
4437  // remaining arguments go into GPRs and then the parameter save area.
4438  // Unnamed arguments for vararg functions always go to GPRs and
4439  // then the parameter save area. For now, put all arguments to vararg
4440  // routines always in both locations (FPR *and* GPR or stack slot).
4441  bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4442 
4443  // First load the argument into the next available FPR.
4444  if (FPR_idx != NumFPRs)
4445  RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4446 
4447  // Next, load the argument into GPR or stack slot if needed.
4448  if (!NeedGPROrStack)
4449  ;
4450  else if (GPR_idx != NumGPRs) {
4451  // In the non-vararg case, this can only ever happen in the
4452  // presence of f32 array types, since otherwise we never run
4453  // out of FPRs before running out of GPRs.
4454  SDValue ArgVal;
4455 
4456  // Double values are always passed in a single GPR.
4457  if (Arg.getValueType() != MVT::f32) {
4458  ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4459 
4460  // Non-array float values are extended and passed in a GPR.
4461  } else if (!Flags.isInConsecutiveRegs()) {
4462  ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4463  ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4464 
4465  // If we have an array of floats, we collect every odd element
4466  // together with its predecessor into one GPR.
4467  } else if (ArgOffset % PtrByteSize != 0) {
4468  SDValue Lo, Hi;
4469  Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4470  Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4471  if (!isLittleEndian)
4472  std::swap(Lo, Hi);
4473  ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4474 
4475  // The final element, if even, goes into the first half of a GPR.
4476  } else if (Flags.isInConsecutiveRegsLast()) {
4477  ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4478  ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4479  if (!isLittleEndian)
4480  ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4481  DAG.getConstant(32, MVT::i32));
4482 
4483  // Non-final even elements are skipped; they will be handled
4484  // together the with subsequent argument on the next go-around.
4485  } else
4486  ArgVal = SDValue();
4487 
4488  if (ArgVal.getNode())
4489  RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4490  } else {
4491  // Single-precision floating-point values are mapped to the
4492  // second (rightmost) word of the stack doubleword.
4493  if (Arg.getValueType() == MVT::f32 &&
4494  !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4495  SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4496  PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4497  }
4498 
4499  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4500  true, isTailCall, false, MemOpChains,
4501  TailCallArguments, dl);
4502  }
4503  // When passing an array of floats, the array occupies consecutive
4504  // space in the argument area; only round up to the next doubleword
4505  // at the end of the array. Otherwise, each float takes 8 bytes.
4506  ArgOffset += (Arg.getValueType() == MVT::f32 &&
4507  Flags.isInConsecutiveRegs()) ? 4 : 8;
4508  if (Flags.isInConsecutiveRegsLast())
4509  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4510  break;
4511  }
4512  case MVT::v4f32:
4513  case MVT::v4i32:
4514  case MVT::v8i16:
4515  case MVT::v16i8:
4516  case MVT::v2f64:
4517  case MVT::v2i64:
4518  // These can be scalar arguments or elements of a vector array type
4519  // passed directly. The latter are used to implement ELFv2 homogenous
4520  // vector aggregates.
4521 
4522  // For a varargs call, named arguments go into VRs or on the stack as
4523  // usual; unnamed arguments always go to the stack or the corresponding
4524  // GPRs when within range. For now, we always put the value in both
4525  // locations (or even all three).
4526  if (isVarArg) {
4527  // We could elide this store in the case where the object fits
4528  // entirely in R registers. Maybe later.
4529  SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4530  MachinePointerInfo(), false, false, 0);
4531  MemOpChains.push_back(Store);
4532  if (VR_idx != NumVRs) {
4533  SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4535  false, false, false, 0);
4536  MemOpChains.push_back(Load.getValue(1));
4537 
4538  unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4539  Arg.getSimpleValueType() == MVT::v2i64) ?
4540  VSRH[VR_idx] : VR[VR_idx];
4541  ++VR_idx;
4542 
4543  RegsToPass.push_back(std::make_pair(VReg, Load));
4544  }
4545  ArgOffset += 16;
4546  for (unsigned i=0; i<16; i+=PtrByteSize) {
4547  if (GPR_idx == NumGPRs)
4548  break;
4549  SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4550  DAG.getConstant(i, PtrVT));
4551  SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4552  false, false, false, 0);
4553  MemOpChains.push_back(Load.getValue(1));
4554  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4555  }
4556  break;
4557  }
4558 
4559  // Non-varargs Altivec params go into VRs or on the stack.
4560  if (VR_idx != NumVRs) {
4561  unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4562  Arg.getSimpleValueType() == MVT::v2i64) ?
4563  VSRH[VR_idx] : VR[VR_idx];
4564  ++VR_idx;
4565 
4566  RegsToPass.push_back(std::make_pair(VReg, Arg));
4567  } else {
4568  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4569  true, isTailCall, true, MemOpChains,
4570  TailCallArguments, dl);
4571  }
4572  ArgOffset += 16;
4573  break;
4574  }
4575  }
4576 
4577  assert(NumBytesActuallyUsed == ArgOffset);
4578  (void)NumBytesActuallyUsed;
4579 
4580  if (!MemOpChains.empty())
4581  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4582 
4583  // Check if this is an indirect call (MTCTR/BCTRL).
4584  // See PrepareCall() for more information about calls through function
4585  // pointers in the 64-bit SVR4 ABI.
4586  if (!isTailCall &&
4587  !dyn_cast<GlobalAddressSDNode>(Callee) &&
4588  !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4589  // Load r2 into a virtual register and store it to the TOC save area.
4590  SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4591  // TOC save area offset.
4592  unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4593  SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4594  SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4595  Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4596  false, false, 0);
4597  // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4598  // This does not mean the MTCTR instruction must use R12; it's easier
4599  // to model this as an extra parameter, so do that.
4600  if (isELFv2ABI)
4601  RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4602  }
4603 
4604  // Build a sequence of copy-to-reg nodes chained together with token chain
4605  // and flag operands which copy the outgoing args into the appropriate regs.
4606  SDValue InFlag;
4607  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4608  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4609  RegsToPass[i].second, InFlag);
4610  InFlag = Chain.getValue(1);
4611  }
4612 
4613  if (isTailCall)
4614  PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4615  FPOp, true, TailCallArguments);
4616 
4617  return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4618  RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4619  Ins, InVals);
4620 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
static const MCPhysReg * GetFPR()
SDValue getValue(unsigned R) const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
static void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
unsigned getByValSize() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
static unsigned EnsureStackAlignment(const TargetMachine &Target, unsigned NumBytes)
static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
bool isLittleEndian() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SimpleValueType SimpleTy
virtual MVT getPointerTy(uint32_t=0) const
bool isInConsecutiveRegs() const
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const PPCSubtarget & Subtarget
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
bool isInConsecutiveRegsLast() const
SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) const
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< SDValue > &InVals) const
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, SDLoc dl)
static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
bool isELFv2ABI() const
FIXME: Should use a command-line option.
Definition: PPCSubtarget.h:231
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
SDValue getStackArgumentTokenFactor(SDValue Chain)
const TargetMachine & getTarget() const
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, SDLoc dl) const
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
static unsigned getTOCSaveOffset(bool isELFv2ABI)
std::string Options
Definition: llvm-ar.cpp:73
SDValue PPCTargetLowering::LowerCall_Darwin ( SDValue  Chain,
SDValue  Callee,
CallingConv::ID  CallConv,
bool  isVarArg,
bool  isTailCall,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 4623 of file PPCISelLowering.cpp.

4630  {
4631 
4632  unsigned NumOps = Outs.size();
4633 
4634  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4635  bool isPPC64 = PtrVT == MVT::i64;
4636  unsigned PtrByteSize = isPPC64 ? 8 : 4;
4637 
4638  MachineFunction &MF = DAG.getMachineFunction();
4639 
4640  // Mark this function as potentially containing a function that contains a
4641  // tail call. As a consequence the frame pointer will be used for dynamicalloc
4642  // and restoring the callers stack pointer in this functions epilog. This is
4643  // done because by tail calling the called function might overwrite the value
4644  // in this function's (MF) stack pointer stack slot 0(SP).
4645  if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4647  MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4648 
4649  // Count how many bytes are to be pushed on the stack, including the linkage
4650  // area, and parameter passing area. We start with 24/48 bytes, which is
4651  // prereserved space for [SP][CR][LR][3 x unused].
4652  unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4653  false);
4654  unsigned NumBytes = LinkageSize;
4655 
4656  // Add up all the space actually used.
4657  // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4658  // they all go in registers, but we must reserve stack space for them for
4659  // possible use by the caller. In varargs or 64-bit calls, parameters are
4660  // assigned stack space in order, with padding so Altivec parameters are
4661  // 16-byte aligned.
4662  unsigned nAltivecParamsAtEnd = 0;
4663  for (unsigned i = 0; i != NumOps; ++i) {
4664  ISD::ArgFlagsTy Flags = Outs[i].Flags;
4665  EVT ArgVT = Outs[i].VT;
4666  // Varargs Altivec parameters are padded to a 16 byte boundary.
4667  if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4668  ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4669  ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4670  if (!isVarArg && !isPPC64) {
4671  // Non-varargs Altivec parameters go after all the non-Altivec
4672  // parameters; handle those later so we know how much padding we need.
4673  nAltivecParamsAtEnd++;
4674  continue;
4675  }
4676  // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4677  NumBytes = ((NumBytes+15)/16)*16;
4678  }
4679  NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4680  }
4681 
4682  // Allow for Altivec parameters at the end, if needed.
4683  if (nAltivecParamsAtEnd) {
4684  NumBytes = ((NumBytes+15)/16)*16;
4685  NumBytes += 16*nAltivecParamsAtEnd;
4686  }
4687 
4688  // The prolog code of the callee may store up to 8 GPR argument registers to
4689  // the stack, allowing va_start to index over them in memory if its varargs.
4690  // Because we cannot tell if this is needed on the caller side, we have to
4691  // conservatively assume that it is needed. As such, make sure we have at
4692  // least enough stack space for the caller to store the 8 GPRs.
4693  NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4694 
4695  // Tail call needs the stack to be aligned.
4696  if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4698  NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4699 
4700  // Calculate by how many bytes the stack has to be adjusted in case of tail
4701  // call optimization.
4702  int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4703 
4704  // To protect arguments on the stack from being clobbered in a tail call,
4705  // force all the loads to happen before doing any other lowering.
4706  if (isTailCall)
4707  Chain = DAG.getStackArgumentTokenFactor(Chain);
4708 
4709  // Adjust the stack pointer for the new arguments...
4710  // These operations are automatically eliminated by the prolog/epilog pass
4711  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4712  dl);
4713  SDValue CallSeqStart = Chain;
4714 
4715  // Load the return address and frame pointer so it can be move somewhere else
4716  // later.
4717  SDValue LROp, FPOp;
4718  Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4719  dl);
4720 
4721  // Set up a copy of the stack pointer for use loading and storing any
4722  // arguments that may not fit in the registers available for argument
4723  // passing.
4724  SDValue StackPtr;
4725  if (isPPC64)
4726  StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4727  else
4728  StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4729 
4730  // Figure out which arguments are going to go in registers, and which in
4731  // memory. Also, if this is a vararg function, floating point operations
4732  // must be stored to our stack, and loaded into integer regs as well, if
4733  // any integer regs are available for argument passing.
4734  unsigned ArgOffset = LinkageSize;
4735  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4736 
4737  static const MCPhysReg GPR_32[] = { // 32-bit registers.
4738  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4739  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4740  };
4741  static const MCPhysReg GPR_64[] = { // 64-bit registers.
4742  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4743  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4744  };
4745  static const MCPhysReg *FPR = GetFPR();
4746 
4747  static const MCPhysReg VR[] = {
4748  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4749  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4750  };
4751  const unsigned NumGPRs = array_lengthof(GPR_32);
4752  const unsigned NumFPRs = 13;
4753  const unsigned NumVRs = array_lengthof(VR);
4754 
4755  const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4756 
4758  SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4759 
4760  SmallVector<SDValue, 8> MemOpChains;
4761  for (unsigned i = 0; i != NumOps; ++i) {
4762  SDValue Arg = OutVals[i];
4763  ISD::ArgFlagsTy Flags = Outs[i].Flags;
4764 
4765  // PtrOff will be used to store the current argument to the stack if a
4766  // register cannot be found for it.
4767  SDValue PtrOff;
4768 
4769  PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4770 
4771  PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4772 
4773  // On PPC64, promote integers to 64-bit values.
4774  if (isPPC64 && Arg.getValueType() == MVT::i32) {
4775  // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4776  unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4777  Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4778  }
4779 
4780  // FIXME memcpy is used way more than necessary. Correctness first.
4781  // Note: "by value" is code for passing a structure by value, not
4782  // basic types.
4783  if (Flags.isByVal()) {
4784  unsigned Size = Flags.getByValSize();
4785  // Very small objects are passed right-justified. Everything else is
4786  // passed left-justified.
4787  if (Size==1 || Size==2) {
4788  EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4789  if (GPR_idx != NumGPRs) {
4790  SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4791  MachinePointerInfo(), VT,
4792  false, false, 0);
4793  MemOpChains.push_back(Load.getValue(1));
4794  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4795 
4796  ArgOffset += PtrByteSize;
4797  } else {
4798  SDValue Const = DAG.getConstant(PtrByteSize - Size,
4799  PtrOff.getValueType());
4800  SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4801  Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4802  CallSeqStart,
4803  Flags, DAG, dl);
4804  ArgOffset += PtrByteSize;
4805  }
4806  continue;
4807  }
4808  // Copy entire object into memory. There are cases where gcc-generated
4809  // code assumes it is there, even if it could be put entirely into
4810  // registers. (This is not what the doc says.)
4811  Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4812  CallSeqStart,
4813  Flags, DAG, dl);
4814 
4815  // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4816  // copy the pieces of the object that fit into registers from the
4817  // parameter save area.
4818  for (unsigned j=0; j<Size; j+=PtrByteSize) {
4819  SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4820  SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4821  if (GPR_idx != NumGPRs) {
4822  SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4824  false, false, false, 0);
4825  MemOpChains.push_back(Load.getValue(1));
4826  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4827  ArgOffset += PtrByteSize;
4828  } else {
4829  ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4830  break;
4831  }
4832  }
4833  continue;
4834  }
4835 
4836  switch (Arg.getSimpleValueType().SimpleTy) {
4837  default: llvm_unreachable("Unexpected ValueType for argument!");
4838  case MVT::i1:
4839  case MVT::i32:
4840  case MVT::i64:
4841  if (GPR_idx != NumGPRs) {
4842  if (Arg.getValueType() == MVT::i1)
4843  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4844 
4845  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4846  } else {
4847  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4848  isPPC64, isTailCall, false, MemOpChains,
4849  TailCallArguments, dl);
4850  }
4851  ArgOffset += PtrByteSize;
4852  break;
4853  case MVT::f32:
4854  case MVT::f64:
4855  if (FPR_idx != NumFPRs) {
4856  RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4857 
4858  if (isVarArg) {
4859  SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4860  MachinePointerInfo(), false, false, 0);
4861  MemOpChains.push_back(Store);
4862 
4863  // Float varargs are always shadowed in available integer registers
4864  if (GPR_idx != NumGPRs) {
4865  SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4866  MachinePointerInfo(), false, false,
4867  false, 0);
4868  MemOpChains.push_back(Load.getValue(1));
4869  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4870  }
4871  if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4872  SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4873  PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4874  SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4876  false, false, false, 0);
4877  MemOpChains.push_back(Load.getValue(1));
4878  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4879  }
4880  } else {
4881  // If we have any FPRs remaining, we may also have GPRs remaining.
4882  // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4883  // GPRs.
4884  if (GPR_idx != NumGPRs)
4885  ++GPR_idx;
4886  if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4887  !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4888  ++GPR_idx;
4889  }
4890  } else
4891  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4892  isPPC64, isTailCall, false, MemOpChains,
4893  TailCallArguments, dl);
4894  if (isPPC64)
4895  ArgOffset += 8;
4896  else
4897  ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4898  break;
4899  case MVT::v4f32:
4900  case MVT::v4i32:
4901  case MVT::v8i16:
4902  case MVT::v16i8:
4903  if (isVarArg) {
4904  // These go aligned on the stack, or in the corresponding R registers
4905  // when within range. The Darwin PPC ABI doc claims they also go in
4906  // V registers; in fact gcc does this only for arguments that are
4907  // prototyped, not for those that match the ... We do it for all
4908  // arguments, seems to work.
4909  while (ArgOffset % 16 !=0) {
4910  ArgOffset += PtrByteSize;
4911  if (GPR_idx != NumGPRs)
4912  GPR_idx++;
4913  }
4914  // We could elide this store in the case where the object fits
4915  // entirely in R registers. Maybe later.
4916  PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4917  DAG.getConstant(ArgOffset, PtrVT));
4918  SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4919  MachinePointerInfo(), false, false, 0);
4920  MemOpChains.push_back(Store);
4921  if (VR_idx != NumVRs) {
4922  SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4924  false, false, false, 0);
4925  MemOpChains.push_back(Load.getValue(1));
4926  RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4927  }
4928  ArgOffset += 16;
4929  for (unsigned i=0; i<16; i+=PtrByteSize) {
4930  if (GPR_idx == NumGPRs)
4931  break;
4932  SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4933  DAG.getConstant(i, PtrVT));
4934  SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4935  false, false, false, 0);
4936  MemOpChains.push_back(Load.getValue(1));
4937  RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4938  }
4939  break;
4940  }
4941 
4942  // Non-varargs Altivec params generally go in registers, but have
4943  // stack space allocated at the end.
4944  if (VR_idx != NumVRs) {
4945  // Doesn't have GPR space allocated.
4946  RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4947  } else if (nAltivecParamsAtEnd==0) {
4948  // We are emitting Altivec params in order.
4949  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4950  isPPC64, isTailCall, true, MemOpChains,
4951  TailCallArguments, dl);
4952  ArgOffset += 16;
4953  }
4954  break;
4955  }
4956  }
4957  // If all Altivec parameters fit in registers, as they usually do,
4958  // they get stack space following the non-Altivec parameters. We
4959  // don't track this here because nobody below needs it.
4960  // If there are more Altivec parameters than fit in registers emit
4961  // the stores here.
4962  if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4963  unsigned j = 0;
4964  // Offset is aligned; skip 1st 12 params which go in V registers.
4965  ArgOffset = ((ArgOffset+15)/16)*16;
4966  ArgOffset += 12*16;
4967  for (unsigned i = 0; i != NumOps; ++i) {
4968  SDValue Arg = OutVals[i];
4969  EVT ArgType = Outs[i].VT;
4970  if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4971  ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4972  if (++j > NumVRs) {
4973  SDValue PtrOff;
4974  // We are emitting Altivec params in order.
4975  LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4976  isPPC64, isTailCall, true, MemOpChains,
4977  TailCallArguments, dl);
4978  ArgOffset += 16;
4979  }
4980  }
4981  }
4982  }
4983 
4984  if (!MemOpChains.empty())
4985  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4986 
4987  // On Darwin, R12 must contain the address of an indirect callee. This does
4988  // not mean the MTCTR instruction must use R12; it's easier to model this as
4989  // an extra parameter, so do that.
4990  if (!isTailCall &&
4991  !dyn_cast<GlobalAddressSDNode>(Callee) &&
4992  !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4993  !isBLACompatibleAddress(Callee, DAG))
4994  RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4995  PPC::R12), Callee));
4996 
4997  // Build a sequence of copy-to-reg nodes chained together with token chain
4998  // and flag operands which copy the outgoing args into the appropriate regs.
4999  SDValue InFlag;
5000  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5001  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5002  RegsToPass[i].second, InFlag);
5003  InFlag = Chain.getValue(1);
5004  }
5005 
5006  if (isTailCall)
5007  PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5008  FPOp, true, TailCallArguments);
5009 
5010  return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5011  RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5012  Ins, InVals);
5013 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
static const MCPhysReg * GetFPR()
SDValue getValue(unsigned R) const
#define R4(n)
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
static void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
unsigned getByValSize() const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
static unsigned EnsureStackAlignment(const TargetMachine &Target, unsigned NumBytes)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SimpleValueType SimpleTy
virtual MVT getPointerTy(uint32_t=0) const
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl) const
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< SDValue > &InVals) const
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, SDLoc dl)
static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
#define R6(n)
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
static SDNode * isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getStackArgumentTokenFactor(SDValue Chain)
const TargetMachine & getTarget() const
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, SDLoc dl) const
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
std::string Options
Definition: llvm-ar.cpp:73
SDValue PPCTargetLowering::LowerCallResult ( SDValue  Chain,
SDValue  InFlag,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 3721 of file PPCISelLowering.cpp.

3725  {
3726 
3728  CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3729  getTargetMachine(), RVLocs, *DAG.getContext());
3730  CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3731 
3732  // Copy all of the result registers out of their specified physreg.
3733  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3734  CCValAssign &VA = RVLocs[i];
3735  assert(VA.isRegLoc() && "Can only return in registers!");
3736 
3737  SDValue Val = DAG.getCopyFromReg(Chain, dl,
3738  VA.getLocReg(), VA.getLocVT(), InFlag);
3739  Chain = Val.getValue(1);
3740  InFlag = Val.getValue(2);
3741 
3742  switch (VA.getLocInfo()) {
3743  default: llvm_unreachable("Unknown loc info!");
3744  case CCValAssign::Full: break;
3745  case CCValAssign::AExt:
3746  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3747  break;
3748  case CCValAssign::ZExt:
3749  Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3750  DAG.getValueType(VA.getValVT()));
3751  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3752  break;
3753  case CCValAssign::SExt:
3754  Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3755  DAG.getValueType(VA.getValVT()));
3756  Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3757  break;
3758  }
3759 
3760  InVals.push_back(Val);
3761  }
3762 
3763  return Chain;
3764 }
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
SDValue getValue(unsigned R) const
MVT getValVT() const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
bool isRegLoc() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
unsigned getLocReg() const
assert(Globals.size() > 1)
MVT getLocVT() const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getValueType(EVT)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo CLI) const
inherited

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 7072 of file SelectionDAGBuilder.cpp.

7072  {
7073  // Handle the incoming return values from the call.
7074  CLI.Ins.clear();
7075  Type *OrigRetTy = CLI.RetTy;
7076  SmallVector<EVT, 4> RetTys;
7077  SmallVector<uint64_t, 4> Offsets;
7078  ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7079 
7081  GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7082 
7083  bool CanLowerReturn =
7084  this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7085  CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7086 
7087  SDValue DemoteStackSlot;
7088  int DemoteStackIdx = -100;
7089  if (!CanLowerReturn) {
7090  // FIXME: equivalent assert?
7091  // assert(!CS.hasInAllocaArgument() &&
7092  // "sret demotion is incompatible with inalloca");
7093  uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7094  unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7096  DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7097  Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7098 
7099  DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7100  ArgListEntry Entry;
7101  Entry.Node = DemoteStackSlot;
7102  Entry.Ty = StackSlotPtrType;
7103  Entry.isSExt = false;
7104  Entry.isZExt = false;
7105  Entry.isInReg = false;
7106  Entry.isSRet = true;
7107  Entry.isNest = false;
7108  Entry.isByVal = false;
7109  Entry.isReturned = false;
7110  Entry.Alignment = Align;
7111  CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7112  CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7113  } else {
7114  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115  EVT VT = RetTys[I];
7116  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118  for (unsigned i = 0; i != NumRegs; ++i) {
7120  MyFlags.VT = RegisterVT;
7121  MyFlags.ArgVT = VT;
7122  MyFlags.Used = CLI.IsReturnValueUsed;
7123  if (CLI.RetSExt)
7124  MyFlags.Flags.setSExt();
7125  if (CLI.RetZExt)
7126  MyFlags.Flags.setZExt();
7127  if (CLI.IsInReg)
7128  MyFlags.Flags.setInReg();
7129  CLI.Ins.push_back(MyFlags);
7130  }
7131  }
7132  }
7133 
7134  // Handle all of the outgoing arguments.
7135  CLI.Outs.clear();
7136  CLI.OutVals.clear();
7137  ArgListTy &Args = CLI.getArgs();
7138  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7139  SmallVector<EVT, 4> ValueVTs;
7140  ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7141  Type *FinalType = Args[i].Ty;
7142  if (Args[i].isByVal)
7143  FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7144  bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7145  FinalType, CLI.CallConv, CLI.IsVarArg);
7146  for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7147  ++Value) {
7148  EVT VT = ValueVTs[Value];
7149  Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7150  SDValue Op = SDValue(Args[i].Node.getNode(),
7151  Args[i].Node.getResNo() + Value);
7153  unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7154 
7155  if (Args[i].isZExt)
7156  Flags.setZExt();
7157  if (Args[i].isSExt)
7158  Flags.setSExt();
7159  if (Args[i].isInReg)
7160  Flags.setInReg();
7161  if (Args[i].isSRet)
7162  Flags.setSRet();
7163  if (Args[i].isByVal)
7164  Flags.setByVal();
7165  if (Args[i].isInAlloca) {
7166  Flags.setInAlloca();
7167  // Set the byval flag for CCAssignFn callbacks that don't know about
7168  // inalloca. This way we can know how many bytes we should've allocated
7169  // and how many bytes a callee cleanup function will pop. If we port
7170  // inalloca to more targets, we'll have to add custom inalloca handling
7171  // in the various CC lowering callbacks.
7172  Flags.setByVal();
7173  }
7174  if (Args[i].isByVal || Args[i].isInAlloca) {
7175  PointerType *Ty = cast<PointerType>(Args[i].Ty);
7176  Type *ElementTy = Ty->getElementType();
7177  Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7178  // For ByVal, alignment should come from FE. BE will guess if this
7179  // info is not there but there are cases it cannot get right.
7180  unsigned FrameAlign;
7181  if (Args[i].Alignment)
7182  FrameAlign = Args[i].Alignment;
7183  else
7184  FrameAlign = getByValTypeAlignment(ElementTy);
7185  Flags.setByValAlign(FrameAlign);
7186  }
7187  if (Args[i].isNest)
7188  Flags.setNest();
7189  if (NeedsRegBlock)
7190  Flags.setInConsecutiveRegs();
7191  Flags.setOrigAlign(OriginalAlignment);
7192 
7193  MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7194  unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7195  SmallVector<SDValue, 4> Parts(NumParts);
7196  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7197 
7198  if (Args[i].isSExt)
7199  ExtendKind = ISD::SIGN_EXTEND;
7200  else if (Args[i].isZExt)
7201  ExtendKind = ISD::ZERO_EXTEND;
7202 
7203  // Conservatively only handle 'returned' on non-vectors for now
7204  if (Args[i].isReturned && !Op.getValueType().isVector()) {
7205  assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7206  "unexpected use of 'returned'");
7207  // Before passing 'returned' to the target lowering code, ensure that
7208  // either the register MVT and the actual EVT are the same size or that
7209  // the return value and argument are extended in the same way; in these
7210  // cases it's safe to pass the argument register value unchanged as the
7211  // return register value (although it's at the target's option whether
7212  // to do so)
7213  // TODO: allow code generation to take advantage of partially preserved
7214  // registers rather than clobbering the entire register when the
7215  // parameter extension method is not compatible with the return
7216  // extension method
7217  if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7218  (ExtendKind != ISD::ANY_EXTEND &&
7219  CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7220  Flags.setReturned();
7221  }
7222 
7223  getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7224  CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7225 
7226  for (unsigned j = 0; j != NumParts; ++j) {
7227  // if it isn't first piece, alignment must be 1
7228  ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7229  i < CLI.NumFixedArgs,
7230  i, j*Parts[j].getValueType().getStoreSize());
7231  if (NumParts > 1 && j == 0)
7232  MyFlags.Flags.setSplit();
7233  else if (j != 0)
7234  MyFlags.Flags.setOrigAlign(1);
7235 
7236  // Only mark the end at the last register of the last value.
7237  if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7238  MyFlags.Flags.setInConsecutiveRegsLast();
7239 
7240  CLI.Outs.push_back(MyFlags);
7241  CLI.OutVals.push_back(Parts[j]);
7242  }
7243  }
7244  }
7245 
7246  SmallVector<SDValue, 4> InVals;
7247  CLI.Chain = LowerCall(CLI, InVals);
7248 
7249  // Verify that the target's LowerCall behaved as expected.
7250  assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7251  "LowerCall didn't return a valid chain!");
7252  assert((!CLI.IsTailCall || InVals.empty()) &&
7253  "LowerCall emitted a return value for a tail call!");
7254  assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7255  "LowerCall didn't emit the correct number of values!");
7256 
7257  // For a tail call, the return value is merely live-out and there aren't
7258  // any nodes in the DAG representing it. Return a special value to
7259  // indicate that a tail call has been emitted and no more Instructions
7260  // should be processed in the current block.
7261  if (CLI.IsTailCall) {
7262  CLI.DAG.setRoot(CLI.Chain);
7263  return std::make_pair(SDValue(), SDValue());
7264  }
7265 
7266  DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7267  assert(InVals[i].getNode() &&
7268  "LowerCall emitted a null value!");
7269  assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7270  "LowerCall emitted a value with the wrong type!");
7271  });
7272 
7273  SmallVector<SDValue, 4> ReturnValues;
7274  if (!CanLowerReturn) {
7275  // The instruction result is the result of loading from the
7276  // hidden sret parameter.
7277  SmallVector<EVT, 1> PVTs;
7278  Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7279 
7280  ComputeValueVTs(*this, PtrRetTy, PVTs);
7281  assert(PVTs.size() == 1 && "Pointers should fit in one register");
7282  EVT PtrVT = PVTs[0];
7283 
7284  unsigned NumValues = RetTys.size();
7285  ReturnValues.resize(NumValues);
7286  SmallVector<SDValue, 4> Chains(NumValues);
7287 
7288  for (unsigned i = 0; i < NumValues; ++i) {
7289  SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7290  CLI.DAG.getConstant(Offsets[i], PtrVT));
7291  SDValue L = CLI.DAG.getLoad(
7292  RetTys[i], CLI.DL, CLI.Chain, Add,
7293  MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7294  false, false, 1);
7295  ReturnValues[i] = L;
7296  Chains[i] = L.getValue(1);
7297  }
7298 
7299  CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7300  } else {
7301  // Collect the legal value parts into potentially illegal values
7302  // that correspond to the original function's return values.
7303  ISD::NodeType AssertOp = ISD::DELETED_NODE;
7304  if (CLI.RetSExt)
7305  AssertOp = ISD::AssertSext;
7306  else if (CLI.RetZExt)
7307  AssertOp = ISD::AssertZext;
7308  unsigned CurReg = 0;
7309  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7310  EVT VT = RetTys[I];
7311  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7312  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7313 
7314  ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7315  NumRegs, RegisterVT, VT, nullptr,
7316  AssertOp));
7317  CurReg += NumRegs;
7318  }
7319 
7320  // For a function returning void, there is no return value. We can't create
7321  // such a node, so we just return a null return value in that case. In
7322  // that case, nothing will actually look at the value.
7323  if (ReturnValues.empty())
7324  return std::make_pair(SDValue(), CLI.Chain);
7325  }
7326 
7327  SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7328  CLI.DAG.getVTList(RetTys), ReturnValues);
7329  return std::make_pair(Res, CLI.Chain);
7330 }
void push_back(const T &Elt)
Definition: SmallVector.h:225
SDValue getValue(unsigned R) const
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
unsigned getSizeInBits() const
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
const SDValue & setRoot(SDValue N)
Definition: SelectionDAG.h:333
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MyFlags
Definition: YAMLIOTest.cpp:502
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SmallVector< ISD::InputArg, 32 > Ins
static int Value(bit_value_t V)
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const DomTreeNodeT * Node
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SmallVector< ISD::OutputArg, 32 > Outs
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
void setOrigAlign(unsigned A)
Type * getElementType() const
Definition: DerivedTypes.h:319
SDNode * getNode() const
get the SDNode which holds the desired result
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI)
assert(Globals.size() > 1)
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
const DataLayout * getDataLayout() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual unsigned getByValTypeAlignment(Type *Ty) const
#define DEBUG(X)
std::vector< ArgListEntry > ArgListTy
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
static PointerType * getUnqual(Type *ElementType)
Definition: DerivedTypes.h:456
const char * Args[]
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
MachineFrameInfo * getFrameInfo()
static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI)
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
SmallVector< SDValue, 32 > OutVals
void ComputeValueVTs(const TargetLowering &TLI, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define I(x, y, z)
Definition: MD5.cpp:54
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
SDValue PPCTargetLowering::LowerConstantPool ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1571 of file PPCISelLowering.cpp.

1572  {
1573  EVT PtrVT = Op.getValueType();
1574  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1575  const Constant *C = CP->getConstVal();
1576 
1577  // 64-bit SVR4 ABI code is always position-independent.
1578  // The actual address of the GlobalValue is stored in the TOC.
1579  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1580  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1581  return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1582  DAG.getRegister(PPC::X2, MVT::i64));
1583  }
1584 
1585  unsigned MOHiFlag, MOLoFlag;
1586  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 
1588  if (isPIC && Subtarget.isSVR4ABI()) {
1589  SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1591  SDLoc DL(CP);
1592  return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1593  DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1594  }
1595 
1596  SDValue CPIHi =
1597  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1598  SDValue CPILo =
1599  DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1600  return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1601 }
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
const DataLayout * DL
True if this is a little endian target.
const PPCSubtarget & Subtarget
LLVM Constant Representation.
Definition: Constant.h:41
const Constant * getConstVal() const
static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
unsigned getAlignment() const
SDValue getRegister(unsigned Reg, EVT VT)
virtual const MCExpr* llvm::TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo ,
const MachineBasicBlock ,
unsigned  ,
MCContext  
) const
inlinevirtualinherited

Reimplemented in llvm::X86TargetLowering.

Definition at line 1894 of file TargetLowering.h.

1896  {
1897  llvm_unreachable("Need to implement this hook if target has custom JTIs");
1898  }
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
) const
private

Definition at line 5158 of file PPCISelLowering.cpp.

5160  {
5161  // Get the inputs.
5162  SDValue Chain = Op.getOperand(0);
5163  SDValue Size = Op.getOperand(1);
5164  SDLoc dl(Op);
5165 
5166  // Get the corect type for pointers.
5167  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5168  // Negate the size.
5169  SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5170  DAG.getConstant(0, PtrVT), Size);
5171  // Construct a node for the frame pointer save index.
5172  SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5173  // Build a DYNALLOC node.
5174  SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5175  SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5176  return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5177 }
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getFramePointerFrameIndex(SelectionDAG &DAG) const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5187 of file PPCISelLowering.cpp.

5188  {
5189  SDLoc DL(Op);
5191  Op.getOperand(0), Op.getOperand(1));
5192 }
const DataLayout * DL
True if this is a little endian target.
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5179 of file PPCISelLowering.cpp.

5180  {
5181  SDLoc DL(Op);
5182  return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5184  Op.getOperand(0), Op.getOperand(1));
5185 }
const DataLayout * DL
True if this is a little endian target.
SDVTList getVTList(EVT VT)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue PPCTargetLowering::LowerFLT_ROUNDS_ ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5540 of file PPCISelLowering.cpp.

5541  {
5542  SDLoc dl(Op);
5543  /*
5544  The rounding mode is in bits 30:31 of FPSR, and has the following
5545  settings:
5546  00 Round to nearest
5547  01 Round to 0
5548  10 Round to +inf
5549  11 Round to -inf
5550 
5551  FLT_ROUNDS, on the other hand, expects the following:
5552  -1 Undefined
5553  0 Round to 0
5554  1 Round to nearest
5555  2 Round to +inf
5556  3 Round to -inf
5557 
5558  To perform the conversion, we do:
5559  ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5560  */
5561 
5562  MachineFunction &MF = DAG.getMachineFunction();
5563  EVT VT = Op.getValueType();
5564  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5565 
5566  // Save FP Control Word to register
5567  EVT NodeTys[] = {
5568  MVT::f64, // return register
5569  MVT::Glue // unused in this context
5570  };
5571  SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5572 
5573  // Save FP register to stack slot
5574  int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5575  SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5576  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5577  StackSlot, MachinePointerInfo(), false, false,0);
5578 
5579  // Load FP Control Word from low 32 bits of stack slot.
5580  SDValue Four = DAG.getConstant(4, PtrVT);
5581  SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5582  SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5583  false, false, false, 0);
5584 
5585  // Transform as necessary
5586  SDValue CWD1 =
5587  DAG.getNode(ISD::AND, dl, MVT::i32,
5588  CWD, DAG.getConstant(3, MVT::i32));
5589  SDValue CWD2 =
5590  DAG.getNode(ISD::SRL, dl, MVT::i32,
5591  DAG.getNode(ISD::AND, dl, MVT::i32,
5592  DAG.getNode(ISD::XOR, dl, MVT::i32,
5593  CWD, DAG.getConstant(3, MVT::i32)),
5594  DAG.getConstant(3, MVT::i32)),
5595  DAG.getConstant(1, MVT::i32));
5596 
5597  SDValue RetVal =
5598  DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5599 
5600  return DAG.getNode((VT.getSizeInBits() < 16 ?
5601  ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5602 }
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MachineFrameInfo * getFrameInfo()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue PPCTargetLowering::LowerFormalArguments ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2301 of file PPCISelLowering.cpp.

2307  {
2308  if (Subtarget.isSVR4ABI()) {
2309  if (Subtarget.isPPC64())
2310  return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2311  dl, DAG, InVals);
2312  else
2313  return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2314  dl, DAG, InVals);
2315  } else {
2316  return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2317  dl, DAG, InVals);
2318  }
2319 }
const PPCSubtarget & Subtarget
SDValue LowerFormalArguments_Darwin(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue LowerFormalArguments_64SVR4(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue LowerFormalArguments_32SVR4(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
SDValue PPCTargetLowering::LowerFormalArguments_32SVR4 ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 2322 of file PPCISelLowering.cpp.

2328  {
2329 
2330  // 32-bit SVR4 ABI Stack Frame Layout:
2331  // +-----------------------------------+
2332  // +--> | Back chain |
2333  // | +-----------------------------------+
2334  // | | Floating-point register save area |
2335  // | +-----------------------------------+
2336  // | | General register save area |
2337  // | +-----------------------------------+
2338  // | | CR save word |
2339  // | +-----------------------------------+
2340  // | | VRSAVE save word |
2341  // | +-----------------------------------+
2342  // | | Alignment padding |
2343  // | +-----------------------------------+
2344  // | | Vector register save area |
2345  // | +-----------------------------------+
2346  // | | Local variable space |
2347  // | +-----------------------------------+
2348  // | | Parameter list area |
2349  // | +-----------------------------------+
2350  // | | LR save word |
2351  // | +-----------------------------------+
2352  // SP--> +--- | Back chain |
2353  // +-----------------------------------+
2354  //
2355  // Specifications:
2356  // System V Application Binary Interface PowerPC Processor Supplement
2357  // AltiVec Technology Programming Interface Manual
2358 
2359  MachineFunction &MF = DAG.getMachineFunction();
2360  MachineFrameInfo *MFI = MF.getFrameInfo();
2361  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2362 
2363  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2364  // Potential tail calls could cause overwriting of argument stack slots.
2365  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2367  unsigned PtrByteSize = 4;
2368 
2369  // Assign locations to all of the incoming arguments.
2371  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2372  getTargetMachine(), ArgLocs, *DAG.getContext());
2373 
2374  // Reserve space for the linkage area on the stack.
2375  unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2376  CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2377 
2378  CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2379 
2380  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2381  CCValAssign &VA = ArgLocs[i];
2382 
2383  // Arguments stored in registers.
2384  if (VA.isRegLoc()) {
2385  const TargetRegisterClass *RC;
2386  EVT ValVT = VA.getValVT();
2387 
2388  switch (ValVT.getSimpleVT().SimpleTy) {
2389  default:
2390  llvm_unreachable("ValVT not supported by formal arguments Lowering");
2391  case MVT::i1:
2392  case MVT::i32:
2393  RC = &PPC::GPRCRegClass;
2394  break;
2395  case MVT::f32:
2396  RC = &PPC::F4RCRegClass;
2397  break;
2398  case MVT::f64:
2399  if (Subtarget.hasVSX())
2400  RC = &PPC::VSFRCRegClass;
2401  else
2402  RC = &PPC::F8RCRegClass;
2403  break;
2404  case MVT::v16i8:
2405  case MVT::v8i16:
2406  case MVT::v4i32:
2407  case MVT::v4f32:
2408  RC = &PPC::VRRCRegClass;
2409  break;
2410  case MVT::v2f64:
2411  case MVT::v2i64:
2412  RC = &PPC::VSHRCRegClass;
2413  break;
2414  }
2415 
2416  // Transform the arguments stored in physical registers into virtual ones.
2417  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2418  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2419  ValVT == MVT::i1 ? MVT::i32 : ValVT);
2420 
2421  if (ValVT == MVT::i1)
2422  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2423 
2424  InVals.push_back(ArgValue);
2425  } else {
2426  // Argument stored in memory.
2427  assert(VA.isMemLoc());
2428 
2429  unsigned ArgSize = VA.getLocVT().getStoreSize();
2430  int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2431  isImmutable);
2432 
2433  // Create load nodes to retrieve arguments from the stack.
2434  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2435  InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2437  false, false, false, 0));
2438  }
2439  }
2440 
2441  // Assign locations to all of the incoming aggregate by value arguments.
2442  // Aggregates passed by value are stored in the local variable space of the
2443  // caller's stack frame, right above the parameter list area.
2444  SmallVector<CCValAssign, 16> ByValArgLocs;
2445  CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2446  getTargetMachine(), ByValArgLocs, *DAG.getContext());
2447 
2448  // Reserve stack space for the allocations in CCInfo.
2449  CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2450 
2451  CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2452 
2453  // Area that is at least reserved in the caller of this function.
2454  unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2455  MinReservedArea = std::max(MinReservedArea, LinkageSize);
2456 
2457  // Set the size that is at least reserved in caller of this function. Tail
2458  // call optimized function's reserved stack space needs to be aligned so that
2459  // taking the difference between two stack areas will result in an aligned
2460  // stack.
2461  MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2462  FuncInfo->setMinReservedArea(MinReservedArea);
2463 
2464  SmallVector<SDValue, 8> MemOps;
2465 
2466  // If the function takes variable number of arguments, make a frame index for
2467  // the start of the first vararg value... for expansion of llvm.va_start.
2468  if (isVarArg) {
2469  static const MCPhysReg GPArgRegs[] = {
2470  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2471  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2472  };
2473  const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2474 
2475  static const MCPhysReg FPArgRegs[] = {
2476  PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2477  PPC::F8
2478  };
2479  const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2480 
2481  FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2482  NumGPArgRegs));
2483  FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2484  NumFPArgRegs));
2485 
2486  // Make room for NumGPArgRegs and NumFPArgRegs.
2487  int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2488  NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2489 
2490  FuncInfo->setVarArgsStackOffset(
2491  MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2492  CCInfo.getNextStackOffset(), true));
2493 
2494  FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2495  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2496 
2497  // The fixed integer arguments of a variadic function are stored to the
2498  // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2499  // the result of va_next.
2500  for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2501  // Get an existing live-in vreg, or add a new one.
2502  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2503  if (!VReg)
2504  VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2505 
2506  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2507  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2508  MachinePointerInfo(), false, false, 0);
2509  MemOps.push_back(Store);
2510  // Increment the address by four for the next argument to store
2511  SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2512  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2513  }
2514 
2515  // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2516  // is set.
2517  // The double arguments are stored to the VarArgsFrameIndex
2518  // on the stack.
2519  for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2520  // Get an existing live-in vreg, or add a new one.
2521  unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2522  if (!VReg)
2523  VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2524 
2525  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2526  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2527  MachinePointerInfo(), false, false, 0);
2528  MemOps.push_back(Store);
2529  // Increment the address by eight for the next argument to store
2530  SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2531  PtrVT);
2532  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2533  }
2534  }
2535 
2536  if (!MemOps.empty())
2537  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2538 
2539  return Chain;
2540 }
SDValue getValue(unsigned R) const
MVT getValVT() const
void setVarArgsNumGPR(unsigned Num)
#define R4(n)
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
static unsigned EnsureStackAlignment(const TargetMachine &Target, unsigned NumBytes)
void setVarArgsNumFPR(unsigned Num)
bool isRegLoc() const
void setVarArgsStackOffset(int Offset)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
Abstract Stack Frame Information.
unsigned getStoreSize() const
virtual MVT getPointerTy(uint32_t=0) const
unsigned getLocReg() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const PPCSubtarget & Subtarget
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
MVT getLocVT() const
unsigned getLiveInVirtReg(unsigned PReg) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
void setVarArgsFrameIndex(int Index)
unsigned GuaranteedTailCallOpt
void setMinReservedArea(unsigned size)
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
#define R6(n)
CCValAssign - Represent assignment of one arg/retval to a location.
MachineFrameInfo * getFrameInfo()
bool isMemLoc() const
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
MachineRegisterInfo & getRegInfo()
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool hasVSX() const
Definition: PPCSubtarget.h:209
const TargetMachine & getTarget() const
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
unsigned getLocMemOffset() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
unsigned AllocateStack(unsigned Size, unsigned Align)
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue PPCTargetLowering::LowerFormalArguments_64SVR4 ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 2559 of file PPCISelLowering.cpp.

2565  {
2566  // TODO: add description of PPC stack frame format, or at least some docs.
2567  //
2568  bool isELFv2ABI = Subtarget.isELFv2ABI();
2570  MachineFunction &MF = DAG.getMachineFunction();
2571  MachineFrameInfo *MFI = MF.getFrameInfo();
2572  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2573 
2574  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2575  // Potential tail calls could cause overwriting of argument stack slots.
2576  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2578  unsigned PtrByteSize = 8;
2579 
2580  unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2581  isELFv2ABI);
2582 
2583  static const MCPhysReg GPR[] = {
2584  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2585  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2586  };
2587 
2588  static const MCPhysReg *FPR = GetFPR();
2589 
2590  static const MCPhysReg VR[] = {
2591  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2592  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2593  };
2594  static const MCPhysReg VSRH[] = {
2595  PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2596  PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2597  };
2598 
2599  const unsigned Num_GPR_Regs = array_lengthof(GPR);
2600  const unsigned Num_FPR_Regs = 13;
2601  const unsigned Num_VR_Regs = array_lengthof(VR);
2602 
2603  // Do a first pass over the arguments to determine whether the ABI
2604  // guarantees that our caller has allocated the parameter save area
2605  // on its stack frame. In the ELFv1 ABI, this is always the case;
2606  // in the ELFv2 ABI, it is true if this is a vararg function or if
2607  // any parameter is located in a stack slot.
2608 
2609  bool HasParameterArea = !isELFv2ABI || isVarArg;
2610  unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2611  unsigned NumBytes = LinkageSize;
2612  unsigned AvailableFPRs = Num_FPR_Regs;
2613  unsigned AvailableVRs = Num_VR_Regs;
2614  for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2615  if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2616  PtrByteSize, LinkageSize, ParamAreaSize,
2617  NumBytes, AvailableFPRs, AvailableVRs))
2618  HasParameterArea = true;
2619 
2620  // Add DAG nodes to load the arguments or copy them out of registers. On
2621  // entry to a function on PPC, the arguments start after the linkage area,
2622  // although the first ones are often in registers.
2623 
2624  unsigned ArgOffset = LinkageSize;
2625  unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2626  SmallVector<SDValue, 8> MemOps;
2628  unsigned CurArgIdx = 0;
2629  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2630  SDValue ArgVal;
2631  bool needsLoad = false;
2632  EVT ObjectVT = Ins[ArgNo].VT;
2633  EVT OrigVT = Ins[ArgNo].ArgVT;
2634  unsigned ObjSize = ObjectVT.getStoreSize();
2635  unsigned ArgSize = ObjSize;
2636  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2637  std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2638  CurArgIdx = Ins[ArgNo].OrigArgIndex;
2639 
2640  /* Respect alignment of argument on the stack. */
2641  unsigned Align =
2642  CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2643  ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2644  unsigned CurArgOffset = ArgOffset;
2645 
2646  /* Compute GPR index associated with argument offset. */
2647  GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2648  GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2649 
2650  // FIXME the codegen can be much improved in some cases.
2651  // We do not have to keep everything in memory.
2652  if (Flags.isByVal()) {
2653  // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2654  ObjSize = Flags.getByValSize();
2655  ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2656  // Empty aggregate parameters do not take up registers. Examples:
2657  // struct { } a;
2658  // union { } b;
2659  // int c[0];
2660  // etc. However, we have to provide a place-holder in InVals, so
2661  // pretend we have an 8-byte item at the current address for that
2662  // purpose.
2663  if (!ObjSize) {
2664  int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2665  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2666  InVals.push_back(FIN);
2667  continue;
2668  }
2669 
2670  // Create a stack object covering all stack doublewords occupied
2671  // by the argument. If the argument is (fully or partially) on
2672  // the stack, or if the argument is fully in registers but the
2673  // caller has allocated the parameter save anyway, we can refer
2674  // directly to the caller's stack frame. Otherwise, create a
2675  // local copy in our own frame.
2676  int FI;
2677  if (HasParameterArea ||
2678  ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2679  FI = MFI->CreateFixedObject(ArgSize, ArgOffset, true);
2680  else
2681  FI = MFI->CreateStackObject(ArgSize, Align, false);
2682  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2683 
2684  // Handle aggregates smaller than 8 bytes.
2685  if (ObjSize < PtrByteSize) {
2686  // The value of the object is its address, which differs from the
2687  // address of the enclosing doubleword on big-endian systems.
2688  SDValue Arg = FIN;
2689  if (!isLittleEndian) {
2690  SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2691  Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2692  }
2693  InVals.push_back(Arg);
2694 
2695  if (GPR_idx != Num_GPR_Regs) {
2696  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2697  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2698  SDValue Store;
2699 
2700  if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2701  EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2702  (ObjSize == 2 ? MVT::i16 : MVT::i32));
2703  Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2704  MachinePointerInfo(FuncArg),
2705  ObjType, false, false, 0);
2706  } else {
2707  // For sizes that don't fit a truncating store (3, 5, 6, 7),
2708  // store the whole register as-is to the parameter save area
2709  // slot.
2710  Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2711  MachinePointerInfo(FuncArg),
2712  false, false, 0);
2713  }
2714 
2715  MemOps.push_back(Store);
2716  }
2717  // Whether we copied from a register or not, advance the offset
2718  // into the parameter save area by a full doubleword.
2719  ArgOffset += PtrByteSize;
2720  continue;
2721  }
2722 
2723  // The value of the object is its address, which is the address of
2724  // its first stack doubleword.
2725  InVals.push_back(FIN);
2726 
2727  // Store whatever pieces of the object are in registers to memory.
2728  for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2729  if (GPR_idx == Num_GPR_Regs)
2730  break;
2731 
2732  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2733  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2734  SDValue Addr = FIN;
2735  if (j) {
2736  SDValue Off = DAG.getConstant(j, PtrVT);
2737  Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2738  }
2739  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2740  MachinePointerInfo(FuncArg, j),
2741  false, false, 0);
2742  MemOps.push_back(Store);
2743  ++GPR_idx;
2744  }
2745  ArgOffset += ArgSize;
2746  continue;
2747  }
2748 
2749  switch (ObjectVT.getSimpleVT().SimpleTy) {
2750  default: llvm_unreachable("Unhandled argument type!");
2751  case MVT::i1:
2752  case MVT::i32:
2753  case MVT::i64:
2754  // These can be scalar arguments or elements of an integer array type
2755  // passed directly. Clang may use those instead of "byval" aggregate
2756  // types to avoid forcing arguments to memory unnecessarily.
2757  if (GPR_idx != Num_GPR_Regs) {
2758  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2759  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2760 
2761  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2762  // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2763  // value to MVT::i64 and then truncate to the correct register size.
2764  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2765  } else {
2766  needsLoad = true;
2767  ArgSize = PtrByteSize;
2768  }
2769  ArgOffset += 8;
2770  break;
2771 
2772  case MVT::f32:
2773  case MVT::f64:
2774  // These can be scalar arguments or elements of a float array type
2775  // passed directly. The latter are used to implement ELFv2 homogenous
2776  // float aggregates.
2777  if (FPR_idx != Num_FPR_Regs) {
2778  unsigned VReg;
2779 
2780  if (ObjectVT == MVT::f32)
2781  VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2782  else
2783  VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2784  &PPC::VSFRCRegClass :
2785  &PPC::F8RCRegClass);
2786 
2787  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2788  ++FPR_idx;
2789  } else if (GPR_idx != Num_GPR_Regs) {
2790  // This can only ever happen in the presence of f32 array types,
2791  // since otherwise we never run out of FPRs before running out
2792  // of GPRs.
2793  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2794  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2795 
2796  if (ObjectVT == MVT::f32) {
2797  if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2798  ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2799  DAG.getConstant(32, MVT::i32));
2800  ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2801  }
2802 
2803  ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2804  } else {
2805  needsLoad = true;
2806  }
2807 
2808  // When passing an array of floats, the array occupies consecutive
2809  // space in the argument area; only round up to the next doubleword
2810  // at the end of the array. Otherwise, each float takes 8 bytes.
2811  ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2812  ArgOffset += ArgSize;
2813  if (Flags.isInConsecutiveRegsLast())
2814  ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2815  break;
2816  case MVT::v4f32:
2817  case MVT::v4i32:
2818  case MVT::v8i16:
2819  case MVT::v16i8:
2820  case MVT::v2f64:
2821  case MVT::v2i64:
2822  // These can be scalar arguments or elements of a vector array type
2823  // passed directly. The latter are used to implement ELFv2 homogenous
2824  // vector aggregates.
2825  if (VR_idx != Num_VR_Regs) {
2826  unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2827  MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2828  MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2829  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2830  ++VR_idx;
2831  } else {
2832  needsLoad = true;
2833  }
2834  ArgOffset += 16;
2835  break;
2836  }
2837 
2838  // We need to load the argument to a virtual register if we determined
2839  // above that we ran out of physical registers of the appropriate type.
2840  if (needsLoad) {
2841  if (ObjSize < ArgSize && !isLittleEndian)
2842  CurArgOffset += ArgSize - ObjSize;
2843  int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2844  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2845  ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2846  false, false, false, 0);
2847  }
2848 
2849  InVals.push_back(ArgVal);
2850  }
2851 
2852  // Area that is at least reserved in the caller of this function.
2853  unsigned MinReservedArea;
2854  if (HasParameterArea)
2855  MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2856  else
2857  MinReservedArea = LinkageSize;
2858 
2859  // Set the size that is at least reserved in caller of this function. Tail
2860  // call optimized functions' reserved stack space needs to be aligned so that
2861  // taking the difference between two stack areas will result in an aligned
2862  // stack.
2863  MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2864  FuncInfo->setMinReservedArea(MinReservedArea);
2865 
2866  // If the function takes variable number of arguments, make a frame index for
2867  // the start of the first vararg value... for expansion of llvm.va_start.
2868  if (isVarArg) {
2869  int Depth = ArgOffset;
2870 
2871  FuncInfo->setVarArgsFrameIndex(
2872  MFI->CreateFixedObject(PtrByteSize, Depth, true));
2873  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2874 
2875  // If this function is vararg, store any remaining integer argument regs
2876  // to their spots on the stack so that they may be loaded by deferencing the
2877  // result of va_next.
2878  for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2879  GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2880  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2881  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2882  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2883  MachinePointerInfo(), false, false, 0);
2884  MemOps.push_back(Store);
2885  // Increment the address by four for the next argument to store
2886  SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2887  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2888  }
2889  }
2890 
2891  if (!MemOps.empty())
2892  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2893 
2894  return Chain;
2895 }
static const MCPhysReg * GetFPR()
SDValue getValue(unsigned R) const
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs)
unsigned getByValSize() const
static unsigned EnsureStackAlignment(const TargetMachine &Target, unsigned NumBytes)
static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
const Function * getFunction() const
bool isLittleEndian() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
static void advance(T &it, size_t Val)
SimpleValueType SimpleTy
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
bool isInConsecutiveRegs() const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
const PPCSubtarget & Subtarget
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
bool isInConsecutiveRegsLast() const
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
unsigned getStoreSize() const
Definition: ValueTypes.h:246
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
void setVarArgsFrameIndex(int Index)
unsigned GuaranteedTailCallOpt
arg_iterator arg_begin()
Definition: Function.h:417
bool isELFv2ABI() const
FIXME: Should use a command-line option.
Definition: PPCSubtarget.h:231
void setMinReservedArea(unsigned size)
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MachineFrameInfo * getFrameInfo()
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, SDLoc dl) const
bool hasVSX() const
Definition: PPCSubtarget.h:209
const TargetMachine & getTarget() const
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue PPCTargetLowering::LowerFormalArguments_Darwin ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

Definition at line 2898 of file PPCISelLowering.cpp.

2904  {
2905  // TODO: add description of PPC stack frame format, or at least some docs.
2906  //
2907  MachineFunction &MF = DAG.getMachineFunction();
2908  MachineFrameInfo *MFI = MF.getFrameInfo();
2909  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2910 
2911  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2912  bool isPPC64 = PtrVT == MVT::i64;
2913  // Potential tail calls could cause overwriting of argument stack slots.
2914  bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2916  unsigned PtrByteSize = isPPC64 ? 8 : 4;
2917 
2918  unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2919  false);
2920  unsigned ArgOffset = LinkageSize;
2921  // Area that is at least reserved in caller of this function.
2922  unsigned MinReservedArea = ArgOffset;
2923 
2924  static const MCPhysReg GPR_32[] = { // 32-bit registers.
2925  PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2926  PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2927  };
2928  static const MCPhysReg GPR_64[] = { // 64-bit registers.
2929  PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2930  PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2931  };
2932 
2933  static const MCPhysReg *FPR = GetFPR();
2934 
2935  static const MCPhysReg VR[] = {
2936  PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2937  PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2938  };
2939 
2940  const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2941  const unsigned Num_FPR_Regs = 13;
2942  const unsigned Num_VR_Regs = array_lengthof( VR);
2943 
2944  unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2945 
2946  const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2947 
2948  // In 32-bit non-varargs functions, the stack space for vectors is after the
2949  // stack space for non-vectors. We do not use this space unless we have
2950  // too many vectors to fit in registers, something that only occurs in
2951  // constructed examples:), but we have to walk the arglist to figure
2952  // that out...for the pathological case, compute VecArgOffset as the
2953  // start of the vector parameter area. Computing VecArgOffset is the
2954  // entire point of the following loop.
2955  unsigned VecArgOffset = ArgOffset;
2956  if (!isVarArg && !isPPC64) {
2957  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2958  ++ArgNo) {
2959  EVT ObjectVT = Ins[ArgNo].VT;
2960  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2961 
2962  if (Flags.isByVal()) {
2963  // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2964  unsigned ObjSize = Flags.getByValSize();
2965  unsigned ArgSize =
2966  ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2967  VecArgOffset += ArgSize;
2968  continue;
2969  }
2970 
2971  switch(ObjectVT.getSimpleVT().SimpleTy) {
2972  default: llvm_unreachable("Unhandled argument type!");
2973  case MVT::i1:
2974  case MVT::i32:
2975  case MVT::f32:
2976  VecArgOffset += 4;
2977  break;
2978  case MVT::i64: // PPC64
2979  case MVT::f64:
2980  // FIXME: We are guaranteed to be !isPPC64 at this point.
2981  // Does MVT::i64 apply?
2982  VecArgOffset += 8;
2983  break;
2984  case MVT::v4f32:
2985  case MVT::v4i32:
2986  case MVT::v8i16:
2987  case MVT::v16i8:
2988  // Nothing to do, we're only looking at Nonvector args here.
2989  break;
2990  }
2991  }
2992  }
2993  // We've found where the vector parameter area in memory is. Skip the
2994  // first 12 parameters; these don't use that memory.
2995  VecArgOffset = ((VecArgOffset+15)/16)*16;
2996  VecArgOffset += 12*16;
2997 
2998  // Add DAG nodes to load the arguments or copy them out of registers. On
2999  // entry to a function on PPC, the arguments start after the linkage area,
3000  // although the first ones are often in registers.
3001 
3002  SmallVector<SDValue, 8> MemOps;
3003  unsigned nAltivecParamsAtEnd = 0;
3005  unsigned CurArgIdx = 0;
3006  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3007  SDValue ArgVal;
3008  bool needsLoad = false;
3009  EVT ObjectVT = Ins[ArgNo].VT;
3010  unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3011  unsigned ArgSize = ObjSize;
3012  ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3013  std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3014  CurArgIdx = Ins[ArgNo].OrigArgIndex;
3015 
3016  unsigned CurArgOffset = ArgOffset;
3017 
3018  // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3019  if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3020  ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3021  if (isVarArg || isPPC64) {
3022  MinReservedArea = ((MinReservedArea+15)/16)*16;
3023  MinReservedArea += CalculateStackSlotSize(ObjectVT,
3024  Flags,
3025  PtrByteSize);
3026  } else nAltivecParamsAtEnd++;
3027  } else
3028  // Calculate min reserved area.
3029  MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3030  Flags,
3031  PtrByteSize);
3032 
3033  // FIXME the codegen can be much improved in some cases.
3034  // We do not have to keep everything in memory.
3035  if (Flags.isByVal()) {
3036  // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3037  ObjSize = Flags.getByValSize();
3038  ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3039  // Objects of size 1 and 2 are right justified, everything else is
3040  // left justified. This means the memory address is adjusted forwards.
3041  if (ObjSize==1 || ObjSize==2) {
3042  CurArgOffset = CurArgOffset + (4 - ObjSize);
3043  }
3044  // The value of the object is its address.
3045  int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3046  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3047  InVals.push_back(FIN);
3048  if (ObjSize==1 || ObjSize==2) {
3049  if (GPR_idx != Num_GPR_Regs) {
3050  unsigned VReg;
3051  if (isPPC64)
3052  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3053  else
3054  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3055  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3056  EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3057  SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3058  MachinePointerInfo(FuncArg),
3059  ObjType, false, false, 0);
3060  MemOps.push_back(Store);
3061  ++GPR_idx;
3062  }
3063 
3064  ArgOffset += PtrByteSize;
3065 
3066  continue;
3067  }
3068  for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3069  // Store whatever pieces of the object are in registers
3070  // to memory. ArgOffset will be the address of the beginning
3071  // of the object.
3072  if (GPR_idx != Num_GPR_Regs) {
3073  unsigned VReg;
3074  if (isPPC64)
3075  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3076  else
3077  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3078  int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3079  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3080  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3081  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3082  MachinePointerInfo(FuncArg, j),
3083  false, false, 0);
3084  MemOps.push_back(Store);
3085  ++GPR_idx;
3086  ArgOffset += PtrByteSize;
3087  } else {
3088  ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3089  break;
3090  }
3091  }
3092  continue;
3093  }
3094 
3095  switch (ObjectVT.getSimpleVT().SimpleTy) {
3096  default: llvm_unreachable("Unhandled argument type!");
3097  case MVT::i1:
3098  case MVT::i32:
3099  if (!isPPC64) {
3100  if (GPR_idx != Num_GPR_Regs) {
3101  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3102  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3103 
3104  if (ObjectVT == MVT::i1)
3105  ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3106 
3107  ++GPR_idx;
3108  } else {
3109  needsLoad = true;
3110  ArgSize = PtrByteSize;
3111  }
3112  // All int arguments reserve stack space in the Darwin ABI.
3113  ArgOffset += PtrByteSize;
3114  break;
3115  }
3116  // FALLTHROUGH
3117  case MVT::i64: // PPC64
3118  if (GPR_idx != Num_GPR_Regs) {
3119  unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3120  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3121 
3122  if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3123  // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3124  // value to MVT::i64 and then truncate to the correct register size.
3125  ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3126 
3127  ++GPR_idx;
3128  } else {
3129  needsLoad = true;
3130  ArgSize = PtrByteSize;
3131  }
3132  // All int arguments reserve stack space in the Darwin ABI.
3133  ArgOffset += 8;
3134  break;
3135 
3136  case MVT::f32:
3137  case MVT::f64:
3138  // Every 4 bytes of argument space consumes one of the GPRs available for
3139  // argument passing.
3140  if (GPR_idx != Num_GPR_Regs) {
3141  ++GPR_idx;
3142  if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3143  ++GPR_idx;
3144  }
3145  if (FPR_idx != Num_FPR_Regs) {
3146  unsigned VReg;
3147 
3148  if (ObjectVT == MVT::f32)
3149  VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3150  else
3151  VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3152 
3153  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3154  ++FPR_idx;
3155  } else {
3156  needsLoad = true;
3157  }
3158 
3159  // All FP arguments reserve stack space in the Darwin ABI.
3160  ArgOffset += isPPC64 ? 8 : ObjSize;
3161  break;
3162  case MVT::v4f32:
3163  case MVT::v4i32:
3164  case MVT::v8i16:
3165  case MVT::v16i8:
3166  // Note that vector arguments in registers don't reserve stack space,
3167  // except in varargs functions.
3168  if (VR_idx != Num_VR_Regs) {
3169  unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3170  ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3171  if (isVarArg) {
3172  while ((ArgOffset % 16) != 0) {
3173  ArgOffset += PtrByteSize;
3174  if (GPR_idx != Num_GPR_Regs)
3175  GPR_idx++;
3176  }
3177  ArgOffset += 16;
3178  GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3179  }
3180  ++VR_idx;
3181  } else {
3182  if (!isVarArg && !isPPC64) {
3183  // Vectors go after all the nonvectors.
3184  CurArgOffset = VecArgOffset;
3185  VecArgOffset += 16;
3186  } else {
3187  // Vectors are aligned.
3188  ArgOffset = ((ArgOffset+15)/16)*16;
3189  CurArgOffset = ArgOffset;
3190  ArgOffset += 16;
3191  }
3192  needsLoad = true;
3193  }
3194  break;
3195  }
3196 
3197  // We need to load the argument to a virtual register if we determined above
3198  // that we ran out of physical registers of the appropriate type.
3199  if (needsLoad) {
3200  int FI = MFI->CreateFixedObject(ObjSize,
3201  CurArgOffset + (ArgSize - ObjSize),
3202  isImmutable);
3203  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3204  ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3205  false, false, false, 0);
3206  }
3207 
3208  InVals.push_back(ArgVal);
3209  }
3210 
3211  // Allow for Altivec parameters at the end, if needed.
3212  if (nAltivecParamsAtEnd) {
3213  MinReservedArea = ((MinReservedArea+15)/16)*16;
3214  MinReservedArea += 16*nAltivecParamsAtEnd;
3215  }
3216 
3217  // Area that is at least reserved in the caller of this function.
3218  MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3219 
3220  // Set the size that is at least reserved in caller of this function. Tail
3221  // call optimized functions' reserved stack space needs to be aligned so that
3222  // taking the difference between two stack areas will result in an aligned
3223  // stack.
3224  MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3225  FuncInfo->setMinReservedArea(MinReservedArea);
3226 
3227  // If the function takes variable number of arguments, make a frame index for
3228  // the start of the first vararg value... for expansion of llvm.va_start.
3229  if (isVarArg) {
3230  int Depth = ArgOffset;
3231 
3232  FuncInfo->setVarArgsFrameIndex(
3233  MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3234  Depth, true));
3235  SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3236 
3237  // If this function is vararg, store any remaining integer argument regs
3238  // to their spots on the stack so that they may be loaded by deferencing the
3239  // result of va_next.
3240  for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3241  unsigned VReg;
3242 
3243  if (isPPC64)
3244  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3245  else
3246  VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3247 
3248  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3249  SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3250  MachinePointerInfo(), false, false, 0);
3251  MemOps.push_back(Store);
3252  // Increment the address by four for the next argument to store
3253  SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3254  FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3255  }
3256  }
3257 
3258  if (!MemOps.empty())
3259  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3260 
3261  return Chain;
3262 }
static const MCPhysReg * GetFPR()
SDValue getValue(unsigned R) const
#define R4(n)
static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI, bool isELFv2ABI)
const TargetMachine & getTargetMachine() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
unsigned getByValSize() const
static unsigned EnsureStackAlignment(const TargetMachine &Target, unsigned NumBytes)
const Function * getFunction() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
static void advance(T &it, size_t Val)
SimpleValueType SimpleTy
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
uint16_t MCPhysReg
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
void setVarArgsFrameIndex(int Index)
unsigned GuaranteedTailCallOpt
arg_iterator arg_begin()
Definition: Function.h:417
void setMinReservedArea(unsigned size)
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
#define R6(n)
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, SDLoc dl) const
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
const TargetMachine & getTarget() const
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MVT getSimpleVT() const
Definition: ValueTypes.h:204
SDValue PPCTargetLowering::LowerFP_TO_INT ( SDValue  Op,
SelectionDAG DAG,
SDLoc  dl 
) const
private

Definition at line 5344 of file PPCISelLowering.cpp.

5345  {
5347  SDValue Src = Op.getOperand(0);
5348  if (Src.getValueType() == MVT::f32)
5349  Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5350 
5351  SDValue Tmp;
5352  switch (Op.getSimpleValueType().SimpleTy) {
5353  default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5354  case MVT::i32:
5355  Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5357  PPCISD::FCTIDZ),
5358  dl, MVT::f64, Src);
5359  break;
5360  case MVT::i64:
5362  "i64 FP_TO_UINT is supported only with FPCVT");
5363  Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5365  dl, MVT::f64, Src);
5366  break;
5367  }
5368 
5369  // Convert the FP value to an int value through memory.
5370  bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5372  SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5373  int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5375 
5376  // Emit a store to the stack slot.
5377  SDValue Chain;
5378  if (i32Stack) {
5379  MachineFunction &MF = DAG.getMachineFunction();
5380  MachineMemOperand *MMO =
5382  SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5383  Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5384  DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5385  } else
5386  Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5387  MPI, false, false, 0);
5388 
5389  // Result is a load from the stack slot. If loading 4 bytes, make sure to
5390  // add in a bias.
5391  if (Op.getValueType() == MVT::i32 && !i32Stack) {
5392  FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5393  DAG.getConstant(4, FIPtr.getValueType()));
5394  MPI = MachinePointerInfo();
5395  }
5396 
5397  return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5398  false, false, false, 0);
5399 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
The memory access writes data.
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
SimpleValueType SimpleTy
SDVTList getVTList(EVT VT)
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
bool hasFPCVT() const
Definition: PPCSubtarget.h:206
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
bool hasSTFIWX() const
Definition: PPCSubtarget.h:203
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerFRAMEADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 9086 of file PPCISelLowering.cpp.

9087  {
9088  SDLoc dl(Op);
9089  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9090 
9091  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9092  bool isPPC64 = PtrVT == MVT::i64;
9093 
9094  MachineFunction &MF = DAG.getMachineFunction();
9095  MachineFrameInfo *MFI = MF.getFrameInfo();
9096  MFI->setFrameAddressIsTaken(true);
9097 
9098  // Naked functions never have a frame pointer, and so we use r1. For all
9099  // other functions, this decision must be delayed until during PEI.
9100  unsigned FrameReg;
9103  FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9104  else
9105  FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9106 
9107  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9108  PtrVT);
9109  while (Depth--)
9110  FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9111  FrameAddr, MachinePointerInfo(), false, false,
9112  false, 0);
9113  return FrameAddr;
9114 }
void setFrameAddressIsTaken(bool T)
const Function * getFunction() const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
Naked function.
Definition: Attributes.h:80
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getOperand(unsigned i) const
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
MachineFrameInfo * getFrameInfo()
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
EVT getValueType() const
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerGlobalAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1737 of file PPCISelLowering.cpp.

1738  {
1739  EVT PtrVT = Op.getValueType();
1740  GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1741  SDLoc DL(GSDN);
1742  const GlobalValue *GV = GSDN->getGlobal();
1743 
1744  // 64-bit SVR4 ABI code is always position-independent.
1745  // The actual address of the GlobalValue is stored in the TOC.
1746  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1747  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1748  return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1749  DAG.getRegister(PPC::X2, MVT::i64));
1750  }
1751 
1752  unsigned MOHiFlag, MOLoFlag;
1753  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1754 
1755  if (isPIC && Subtarget.isSVR4ABI()) {
1756  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1757  GSDN->getOffset(),
1759  return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1761  }
1762 
1763  SDValue GAHi =
1764  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1765  SDValue GALo =
1766  DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1767 
1768  SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1769 
1770  // If the global reference is actually to a non-lazy-pointer, we have to do an
1771  // extra load to get the address of the global.
1772  if (MOHiFlag & PPCII::MO_NLP_FLAG)
1773  Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1774  false, false, false, 0);
1775  return Ptr;
1776 }
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
const GlobalValue * getGlobal() const
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
const DataLayout * DL
True if this is a little endian target.
const PPCSubtarget & Subtarget
static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerGlobalTLSAddress ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1644 of file PPCISelLowering.cpp.

1645  {
1646 
1647  // FIXME: TLS addresses currently use medium model code sequences,
1648  // which is the most useful form. Eventually support for small and
1649  // large models could be added if users need it, at the cost of
1650  // additional complexity.
1651  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1652  SDLoc dl(GA);
1653  const GlobalValue *GV = GA->getGlobal();
1654  EVT PtrVT = getPointerTy();
1655  bool is64bit = Subtarget.isPPC64();
1656 
1658 
1659  if (Model == TLSModel::LocalExec) {
1660  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1662  SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1664  SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1665  is64bit ? MVT::i64 : MVT::i32);
1666  SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1667  return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1668  }
1669 
1670  if (Model == TLSModel::InitialExec) {
1671  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1672  SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1673  PPCII::MO_TLS);
1674  SDValue GOTPtr;
1675  if (is64bit) {
1676  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1677  GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1678  PtrVT, GOTReg, TGA);
1679  } else
1680  GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1681  SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1682  PtrVT, TGA, GOTPtr);
1683  return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1684  }
1685 
1686  if (Model == TLSModel::GeneralDynamic) {
1687  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1688  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1689  SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1690  GOTReg, TGA);
1691  SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1692  GOTEntryHi, TGA);
1693 
1694  // We need a chain node, and don't have one handy. The underlying
1695  // call has no side effects, so using the function entry node
1696  // suffices.
1697  SDValue Chain = DAG.getEntryNode();
1698  Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1699  SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1700  SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1701  PtrVT, ParmReg, TGA);
1702  // The return value from GET_TLS_ADDR really is in X3 already, but
1703  // some hacks are needed here to tie everything together. The extra
1704  // copies dissolve during subsequent transforms.
1705  Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1706  return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1707  }
1708 
1709  if (Model == TLSModel::LocalDynamic) {
1710  SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1711  SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1712  SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1713  GOTReg, TGA);
1714  SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1715  GOTEntryHi, TGA);
1716 
1717  // We need a chain node, and don't have one handy. The underlying
1718  // call has no side effects, so using the function entry node
1719  // suffices.
1720  SDValue Chain = DAG.getEntryNode();
1721  Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1722  SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1723  SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1724  PtrVT, ParmReg, TGA);
1725  // The return value from GET_TLSLD_ADDR really is in X3 already, but
1726  // some hacks are needed here to tie everything together. The extra
1727  // copies dissolve during subsequent transforms.
1728  Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1729  SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1730  Chain, ParmReg, TGA);
1731  return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1732  }
1733 
1734  llvm_unreachable("Unknown TLS model!");
1735 }
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
const TargetMachine & getTargetMachine() const
const GlobalValue * getGlobal() const
#define R2(n)
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
virtual MVT getPointerTy(uint32_t=0) const
const PPCSubtarget & Subtarget
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
TLSModel::Model getTLSModel(const GlobalValue *GV) const
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1967 of file PPCISelLowering.cpp.

1968  {
1969  SDValue Chain = Op.getOperand(0);
1970  SDValue Trmp = Op.getOperand(1); // trampoline
1971  SDValue FPtr = Op.getOperand(2); // nested function
1972  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1973  SDLoc dl(Op);
1974 
1975  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1976  bool isPPC64 = (PtrVT == MVT::i64);
1977  Type *IntPtrTy =
1979  *DAG.getContext());
1980 
1983 
1984  Entry.Ty = IntPtrTy;
1985  Entry.Node = Trmp; Args.push_back(Entry);
1986 
1987  // TrampSize == (isPPC64 ? 48 : 40);
1988  Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1989  isPPC64 ? MVT::i64 : MVT::i32);
1990  Args.push_back(Entry);
1991 
1992  Entry.Node = FPtr; Args.push_back(Entry);
1993  Entry.Node = Nest; Args.push_back(Entry);
1994 
1995  // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1997  CLI.setDebugLoc(dl).setChain(Chain)
1998  .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1999  DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2000  std::move(Args), 0);
2001 
2002  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2003  return CallResult.second;
2004 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getExternalSymbol(const char *Sym, EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
const SDValue & getOperand(unsigned i) const
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
const DataLayout * getDataLayout() const
std::vector< ArgListEntry > ArgListTy
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Definition: DataLayout.cpp:703
const char * Args[]
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue PPCTargetLowering::LowerINT_TO_FP ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5401 of file PPCISelLowering.cpp.

5402  {
5403  SDLoc dl(Op);
5404  // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5405  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5406  return SDValue();
5407 
5408  if (Op.getOperand(0).getValueType() == MVT::i1)
5409  return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5410  DAG.getConstantFP(1.0, Op.getValueType()),
5411  DAG.getConstantFP(0.0, Op.getValueType()));
5412 
5414  "UINT_TO_FP is supported only with FPCVT");
5415 
5416  // If we have FCFIDS, then use it when converting to single-precision.
5417  // Otherwise, convert to double-precision and then round.
5418  unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5419  (Op.getOpcode() == ISD::UINT_TO_FP ?
5421  (Op.getOpcode() == ISD::UINT_TO_FP ?
5423  MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5424  MVT::f32 : MVT::f64;
5425 
5426  if (Op.getOperand(0).getValueType() == MVT::i64) {
5427  SDValue SINT = Op.getOperand(0);
5428  // When converting to single-precision, we actually need to convert
5429  // to double-precision first and then round to single-precision.
5430  // To avoid double-rounding effects during that operation, we have
5431  // to prepare the input operand. Bits that might be truncated when
5432  // converting to double-precision are replaced by a bit that won't
5433  // be lost at this stage, but is below the single-precision rounding
5434  // position.
5435  //
5436  // However, if -enable-unsafe-fp-math is in effect, accept double
5437  // rounding to avoid the extra overhead.
5438  if (Op.getValueType() == MVT::f32 &&
5439  !Subtarget.hasFPCVT() &&
5440  !DAG.getTarget().Options.UnsafeFPMath) {
5441 
5442  // Twiddle input to make sure the low 11 bits are zero. (If this
5443  // is the case, we are guaranteed the value will fit into the 53 bit
5444  // mantissa of an IEEE double-precision value without rounding.)
5445  // If any of those low 11 bits were not zero originally, make sure
5446  // bit 12 (value 2048) is set instead, so that the final rounding
5447  // to single-precision gets the correct result.
5448  SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5449  SINT, DAG.getConstant(2047, MVT::i64));
5450  Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5451  Round, DAG.getConstant(2047, MVT::i64));
5452  Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5453  Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5454  Round, DAG.getConstant(-2048, MVT::i64));
5455 
5456  // However, we cannot use that value unconditionally: if the magnitude
5457  // of the input value is small, the bit-twiddling we did above might
5458  // end up visibly changing the output. Fortunately, in that case, we
5459  // don't need to twiddle bits since the original input will convert
5460  // exactly to double-precision floating-point already. Therefore,
5461  // construct a conditional to use the original value if the top 11
5462  // bits are all sign-bit copies, and use the rounded value computed
5463  // above otherwise.
5464  SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5465  SINT, DAG.getConstant(53, MVT::i32));
5466  Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5467  Cond, DAG.getConstant(1, MVT::i64));
5468  Cond = DAG.getSetCC(dl, MVT::i32,
5469  Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5470 
5471  SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5472  }
5473 
5474  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5475  SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5476 
5477  if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5478  FP = DAG.getNode(ISD::FP_ROUND, dl,
5479  MVT::f32, FP, DAG.getIntPtrConstant(0));
5480  return FP;
5481  }
5482 
5483  assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5484  "Unhandled INT_TO_FP type in custom expander!");
5485  // Since we only generate this in 64-bit mode, we can take advantage of
5486  // 64-bit registers. In particular, sign extend the input value into the
5487  // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5488  // then lfd it and fcfid it.
5489  MachineFunction &MF = DAG.getMachineFunction();
5490  MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5491  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5492 
5493  SDValue Ld;
5494  if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5495  int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5496  SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5497 
5498  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5500  false, false, 0);
5501 
5502  assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5503  "Expected an i32 store");
5504  MachineMemOperand *MMO =
5505  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5507  SDValue Ops[] = { Store, FIdx };
5508  Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5510  dl, DAG.getVTList(MVT::f64, MVT::Other),
5511  Ops, MVT::i32, MMO);
5512  } else {
5513  assert(Subtarget.isPPC64() &&
5514  "i32->FP without LFIWAX supported only on PPC64");
5515 
5516  int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5517  SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5518 
5519  SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5520  Op.getOperand(0));
5521 
5522  // STD the extended value into the stack slot.
5523  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5525  false, false, 0);
5526 
5527  // Load the value as a double.
5528  Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5530  false, false, false, 0);
5531  }
5532 
5533  // FCFID it and return it.
5534  SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5535  if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5536  FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5537  return FP;
5538 }
The memory access reads data.
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
bool hasFPCVT() const
Definition: PPCSubtarget.h:206
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
bool hasLFIWAX() const
Definition: PPCSubtarget.h:204
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom lower, do it, otherwise return null.

Definition at line 6210 of file PPCISelLowering.cpp.

6211  {
6212  // If this is a lowered altivec predicate compare, CompareOpc is set to the
6213  // opcode number of the comparison.
6214  SDLoc dl(Op);
6215  int CompareOpc;
6216  bool isDot;
6217  if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6218  return SDValue(); // Don't custom lower most intrinsics.
6219 
6220  // If this is a non-dot comparison, make the VCMP node and we are done.
6221  if (!isDot) {
6222  SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6223  Op.getOperand(1), Op.getOperand(2),
6224  DAG.getConstant(CompareOpc, MVT::i32));
6225  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6226  }
6227 
6228  // Create the PPCISD altivec 'dot' comparison node.
6229  SDValue Ops[] = {
6230  Op.getOperand(2), // LHS
6231  Op.getOperand(3), // RHS
6232  DAG.getConstant(CompareOpc, MVT::i32)
6233  };
6234  EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6235  SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6236 
6237  // Now that we have the comparison, emit a copy from the CR to a GPR.
6238  // This is flagged to the above dot comparison.
6240  DAG.getRegister(PPC::CR6, MVT::i32),
6241  CompNode.getValue(1));
6242 
6243  // Unpack the result based on how the target uses it.
6244  unsigned BitNo; // Bit # of CR6.
6245  bool InvertBit; // Invert result?
6246  switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6247  default: // Can't happen, don't crash on invalid number though.
6248  case 0: // Return the value of the EQ bit of CR6.
6249  BitNo = 0; InvertBit = false;
6250  break;
6251  case 1: // Return the inverted value of the EQ bit of CR6.
6252  BitNo = 0; InvertBit = true;
6253  break;
6254  case 2: // Return the value of the LT bit of CR6.
6255  BitNo = 2; InvertBit = false;
6256  break;
6257  case 3: // Return the inverted value of the LT bit of CR6.
6258  BitNo = 2; InvertBit = true;
6259  break;
6260  }
6261 
6262  // Shift the bit into the low position.
6263  Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6264  DAG.getConstant(8-(3-BitNo), MVT::i32));
6265  // Isolate the bit.
6266  Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6267  DAG.getConstant(1, MVT::i32));
6268 
6269  // If we are supposed to, toggle the bit.
6270  if (InvertBit)
6271  Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6272  DAG.getConstant(1, MVT::i32));
6273  return Flags;
6274 }
SDValue getValue(unsigned R) const
static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue PPCTargetLowering::LowerJumpTable ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1603 of file PPCISelLowering.cpp.

1603  {
1604  EVT PtrVT = Op.getValueType();
1605  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1606 
1607  // 64-bit SVR4 ABI code is always position-independent.
1608  // The actual address of the GlobalValue is stored in the TOC.
1609  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1610  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1611  return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1612  DAG.getRegister(PPC::X2, MVT::i64));
1613  }
1614 
1615  unsigned MOHiFlag, MOLoFlag;
1616  bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1617 
1618  if (isPIC && Subtarget.isSVR4ABI()) {
1619  SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1621  SDLoc DL(GA);
1622  return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1623  DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1624  }
1625 
1626  SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1627  SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1628  return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1629 }
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
const DataLayout * DL
True if this is a little endian target.
const PPCSubtarget & Subtarget
static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:444
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getRegister(unsigned Reg, EVT VT)
SDValue PPCTargetLowering::LowerLOAD ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5194 of file PPCISelLowering.cpp.

5194  {
5195  assert(Op.getValueType() == MVT::i1 &&
5196  "Custom lowering only for i1 loads");
5197 
5198  // First, load 8 bits into 32 bits, then truncate to 1 bit.
5199 
5200  SDLoc dl(Op);
5201  LoadSDNode *LD = cast<LoadSDNode>(Op);
5202 
5203  SDValue Chain = LD->getChain();
5204  SDValue BasePtr = LD->getBasePtr();
5205  MachineMemOperand *MMO = LD->getMemOperand();
5206 
5207  SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5208  BasePtr, MVT::i8, MMO);
5209  SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5210 
5211  SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5212  return DAG.getMergeValues(Ops, dl);
5213 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
const SDValue & getBasePtr() const
virtual MVT getPointerTy(uint32_t=0) const
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
const SDValue & getChain() const
MachineMemOperand * getMemOperand() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue PPCTargetLowering::LowerMUL ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 6318 of file PPCISelLowering.cpp.

6318  {
6319  SDLoc dl(Op);
6320  if (Op.getValueType() == MVT::v4i32) {
6321  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6322 
6323  SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6324  SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6325 
6326  SDValue RHSSwap = // = vrlw RHS, 16
6327  BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6328 
6329  // Shrinkify inputs to v8i16.
6330  LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6331  RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6332  RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6333 
6334  // Low parts multiplied together, generating 32-bit results (we ignore the
6335  // top parts).
6336  SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6337  LHS, RHS, DAG, dl, MVT::v4i32);
6338 
6339  SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6340  LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6341  // Shift the high parts up 16 bits.
6342  HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6343  Neg16, DAG, dl);
6344  return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6345  } else if (Op.getValueType() == MVT::v8i16) {
6346  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6347 
6348  SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6349 
6350  return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6351  LHS, RHS, Zero, DAG, dl);
6352  } else if (Op.getValueType() == MVT::v16i8) {
6353  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6355 
6356  // Multiply the even 8-bit parts, producing 16-bit sums.
6357  SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6358  LHS, RHS, DAG, dl, MVT::v8i16);
6359  EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6360 
6361  // Multiply the odd 8-bit parts, producing 16-bit sums.
6362  SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6363  LHS, RHS, DAG, dl, MVT::v8i16);
6364  OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6365 
6366  // Merge the results together. Because vmuleub and vmuloub are
6367  // instructions with a big-endian bias, we must reverse the
6368  // element numbering and reverse the meaning of "odd" and "even"
6369  // when generating little endian code.
6370  int Ops[16];
6371  for (unsigned i = 0; i != 8; ++i) {
6372  if (isLittleEndian) {
6373  Ops[i*2 ] = 2*i;
6374  Ops[i*2+1] = 2*i+16;
6375  } else {
6376  Ops[i*2 ] = 2*i+1;
6377  Ops[i*2+1] = 2*i+1+16;
6378  }
6379  }
6380  if (isLittleEndian)
6381  return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6382  else
6383  return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6384  } else {
6385  llvm_unreachable("Unknown mul to lower!");
6386  }
6387 }
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
bool isLittleEndian() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
const SDValue & getOperand(unsigned i) const
static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, SDLoc dl)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue PPCTargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG DAG 
) const
overridevirtual

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 6391 of file PPCISelLowering.cpp.

6391  {
6392  switch (Op.getOpcode()) {
6393  default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6394  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6395  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6396  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6397  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6398  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6399  case ISD::SETCC: return LowerSETCC(Op, DAG);
6400  case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6401  case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6402  case ISD::VASTART:
6403  return LowerVASTART(Op, DAG, Subtarget);
6404 
6405  case ISD::VAARG:
6406  return LowerVAARG(Op, DAG, Subtarget);
6407 
6408  case ISD::VACOPY:
6409  return LowerVACOPY(Op, DAG, Subtarget);
6410 
6411  case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6413  return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6414 
6415  case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6416  case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6417 
6418  case ISD::LOAD: return LowerLOAD(Op, DAG);
6419  case ISD::STORE: return LowerSTORE(Op, DAG);
6420  case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6421  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6422  case ISD::FP_TO_UINT:
6423  case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6424  SDLoc(Op));
6425  case ISD::UINT_TO_FP:
6426  case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6427  case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6428 
6429  // Lower 64-bit shifts.
6430  case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6431  case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6432  case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6433 
6434  // Vector-related lowering.
6435  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6436  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6437  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6438  case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6439  case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6440  case ISD::MUL: return LowerMUL(Op, DAG);
6441 
6442  // For counter-based loop handling.
6443  case ISD::INTRINSIC_W_CHAIN: return SDValue();
6444 
6445  // Frame & Return address.
6446  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6447  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6448  }
6449 }
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
const PPCSubtarget & Subtarget
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
void TargetLowering::LowerOperationWrapper ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
virtualinherited

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 7332 of file SelectionDAGBuilder.cpp.

7334  {
7335  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7336  if (Res.getNode())
7337  Results.push_back(Res);
7338 }
SDNode * getNode() const
get the SDNode which holds the desired result
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
SDValue PPCTargetLowering::LowerReturn ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
SDLoc  dl,
SelectionDAG DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 5027 of file PPCISelLowering.cpp.

5031  {
5032 
5034  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5035  getTargetMachine(), RVLocs, *DAG.getContext());
5036  CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5037 
5038  SDValue Flag;
5039  SmallVector<SDValue, 4> RetOps(1, Chain);
5040 
5041  // Copy the result values into the output registers.
5042  for (unsigned i = 0; i != RVLocs.size(); ++i) {
5043  CCValAssign &VA = RVLocs[i];
5044  assert(VA.isRegLoc() && "Can only return in registers!");
5045 
5046  SDValue Arg = OutVals[i];
5047 
5048  switch (VA.getLocInfo()) {
5049  default: llvm_unreachable("Unknown loc info!");
5050  case CCValAssign::Full: break;
5051  case CCValAssign::AExt:
5052  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5053  break;
5054  case CCValAssign::ZExt:
5055  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5056  break;
5057  case CCValAssign::SExt:
5058  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5059  break;
5060  }
5061 
5062  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5063  Flag = Chain.getValue(1);
5064  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5065  }
5066 
5067  RetOps[0] = Chain; // Update chain.
5068 
5069  // Add the flag if we have it.
5070  if (Flag.getNode())
5071  RetOps.push_back(Flag);
5072 
5073  return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5074 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
Return with a flag operand, matched by 'blr'.
LocInfo getLocInfo() const
const TargetMachine & getTargetMachine() const
bool isRegLoc() const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
unsigned getLocReg() const
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
MVT getLocVT() const
CCValAssign - Represent assignment of one arg/retval to a location.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue PPCTargetLowering::LowerRETURNADDR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 9049 of file PPCISelLowering.cpp.

9050  {
9051  MachineFunction &MF = DAG.getMachineFunction();
9052  MachineFrameInfo *MFI = MF.getFrameInfo();
9053  MFI->setReturnAddressIsTaken(true);
9054 
9056  return SDValue();
9057 
9058  SDLoc dl(Op);
9059  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9060 
9061  // Make sure the function does not optimize away the store of the RA to
9062  // the stack.
9063  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9064  FuncInfo->setLRStoreRequired();
9065  bool isPPC64 = Subtarget.isPPC64();
9066  bool isDarwinABI = Subtarget.isDarwinABI();
9067 
9068  if (Depth > 0) {
9069  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9070  SDValue Offset =
9071 
9072  DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9073  isPPC64? MVT::i64 : MVT::i32);
9074  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9075  DAG.getNode(ISD::ADD, dl, getPointerTy(),
9076  FrameAddr, Offset),
9077  MachinePointerInfo(), false, false, false, 0);
9078  }
9079 
9080  // Just load the return address off the stack.
9081  SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9082  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9083  RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9084 }
bool isDarwinABI() const
Definition: PPCSubtarget.h:228
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
SDValue getReturnAddrFrameIndex(SelectionDAG &DAG) const
MachineFrameInfo * getFrameInfo()
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
void setReturnAddressIsTaken(bool s)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI)
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 6300 of file PPCISelLowering.cpp.

6301  {
6302  SDLoc dl(Op);
6303  // Create a stack slot that is 16-byte aligned.
6304  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6305  int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6306  EVT PtrVT = getPointerTy();
6307  SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6308 
6309  // Store the input value into Value#0 of the stack slot.
6310  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6311  Op.getOperand(0), FIdx, MachinePointerInfo(),
6312  false, false, 0);
6313  // Load it out.
6314  return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6315  false, false, false, 0);
6316 }
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
Abstract Stack Frame Information.
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getOperand(unsigned i) const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
MachineFrameInfo * getFrameInfo()
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
EVT getValueType() const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue PPCTargetLowering::LowerSELECT_CC ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when possible.

Definition at line 5245 of file PPCISelLowering.cpp.

5245  {
5246  // Not FP? Not a fsel.
5247  if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5249  return Op;
5250 
5251  // We might be able to do better than this under some circumstances, but in
5252  // general, fsel-based lowering of select is a finite-math-only optimization.
5253  // For more information, see section F.3 of the 2.06 ISA specification.
5254  if (!DAG.getTarget().Options.NoInfsFPMath ||
5256  return Op;
5257 
5258  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5259 
5260  EVT ResVT = Op.getValueType();
5261  EVT CmpVT = Op.getOperand(0).getValueType();
5262  SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5263  SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5264  SDLoc dl(Op);
5265 
5266  // If the RHS of the comparison is a 0.0, we don't need to do the
5267  // subtraction at all.
5268  SDValue Sel1;
5269  if (isFloatingPointZero(RHS))
5270  switch (CC) {
5271  default: break; // SETUO etc aren't handled by fsel.
5272  case ISD::SETNE:
5273  std::swap(TV, FV);
5274  case ISD::SETEQ:
5275  if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5276  LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5277  Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5278  if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5279  Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5280  return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5281  DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5282  case ISD::SETULT:
5283  case ISD::SETLT:
5284  std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5285  case ISD::SETOGE:
5286  case ISD::SETGE:
5287  if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5288  LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5289  return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5290  case ISD::SETUGT:
5291  case ISD::SETGT:
5292  std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5293  case ISD::SETOLE:
5294  case ISD::SETLE:
5295  if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5296  LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5297  return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5298  DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5299  }
5300 
5301  SDValue Cmp;
5302  switch (CC) {
5303  default: break; // SETUO etc aren't handled by fsel.
5304  case ISD::SETNE:
5305  std::swap(TV, FV);
5306  case ISD::SETEQ:
5307  Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5308  if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5309  Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5310  Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5311  if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5312  Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5313  return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5314  DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5315  case ISD::SETULT:
5316  case ISD::SETLT:
5317  Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5318  if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5319  Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5320  return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5321  case ISD::SETOGE:
5322  case ISD::SETGE:
5323  Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5324  if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5325  Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5326  return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5327  case ISD::SETUGT:
5328  case ISD::SETGT:
5329  Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5330  if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5331  Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5332  return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5333  case ISD::SETOLE:
5334  case ISD::SETLE:
5335  Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5336  if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5337  Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5338  return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5339  }
5340  return Op;
5341 }
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
static bool isFloatingPointZero(SDValue Op)
isFloatingPointZero - Return true if this is 0.0 or -0.0.
const SDValue & getOperand(unsigned i) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
SDValue PPCTargetLowering::LowerSETCC ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 1778 of file PPCISelLowering.cpp.

1778  {
1779  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1780  SDLoc dl(Op);
1781 
1782  if (Op.getValueType() == MVT::v2i64) {
1783  // When the operands themselves are v2i64 values, we need to do something
1784  // special because VSX has no underlying comparison operations for these.
1785  if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1786  // Equality can be handled by casting to the legal type for Altivec
1787  // comparisons, everything else needs to be expanded.
1788  if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1789  return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1790  DAG.getSetCC(dl, MVT::v4i32,
1791  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1792  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1793  CC));
1794  }
1795 
1796  return SDValue();
1797  }
1798 
1799  // We handle most of these in the usual way.
1800  return Op;
1801  }
1802 
1803  // If we're comparing for equality to zero, expose the fact that this is
1804  // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1805  // fold the new nodes.
1806  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1807  if (C->isNullValue() && CC == ISD::SETEQ) {
1808  EVT VT = Op.getOperand(0).getValueType();
1809  SDValue Zext = Op.getOperand(0);
1810  if (VT.bitsLT(MVT::i32)) {
1811  VT = MVT::i32;
1812  Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1813  }
1814  unsigned Log2b = Log2_32(VT.getSizeInBits());
1815  SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1816  SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1817  DAG.getConstant(Log2b, MVT::i32));
1818  return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1819  }
1820  // Leave comparisons against 0 and -1 alone for now, since they're usually
1821  // optimized. FIXME: revisit this when we can custom lower all setcc
1822  // optimizations.
1823  if (C->isAllOnesValue() || C->isNullValue())
1824  return SDValue();
1825  }
1826 
1827  // If we have an integer seteq/setne, turn it into a compare against zero
1828  // by xor'ing the rhs with the lhs, which is faster than setting a
1829  // condition register, reading it back out, and masking the correct bit. The
1830  // normal approach here uses sub to do this instead of xor. Using xor exposes
1831  // the result to other bit-twiddling opportunities.
1832  EVT LHSVT = Op.getOperand(0).getValueType();
1833  if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1834  EVT VT = Op.getValueType();
1835  SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1836  Op.getOperand(1));
1837  return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1838  }
1839  return SDValue();
1840 }
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
const SDValue & getOperand(unsigned i) const
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:452
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue PPCTargetLowering::LowerSHL_PARTS ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5604 of file PPCISelLowering.cpp.

5604  {
5605  EVT VT = Op.getValueType();
5606  unsigned BitWidth = VT.getSizeInBits();
5607  SDLoc dl(Op);
5608  assert(Op.getNumOperands() == 3 &&
5609  VT == Op.getOperand(1).getValueType() &&
5610  "Unexpected SHL!");
5611 
5612  // Expand into a bunch of logical ops. Note that these ops
5613  // depend on the PPC behavior for oversized shift amounts.
5614  SDValue Lo = Op.getOperand(0);
5615  SDValue Hi = Op.getOperand(1);
5616  SDValue Amt = Op.getOperand(2);
5617  EVT AmtVT = Amt.getValueType();
5618 
5619  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5620  DAG.getConstant(BitWidth, AmtVT), Amt);
5621  SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5622  SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5623  SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5624  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5625  DAG.getConstant(-BitWidth, AmtVT));
5626  SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5627  SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5628  SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5629  SDValue OutOps[] = { OutLo, OutHi };
5630  return DAG.getMergeValues(OutOps, dl);
5631 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
unsigned getNumOperands() const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 6276 of file PPCISelLowering.cpp.

6277  {
6278  SDLoc dl(Op);
6279  // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6280  // instructions), but for smaller types, we need to first extend up to v2i32
6281  // before doing going farther.
6282  if (Op.getValueType() == MVT::v2i64) {
6283  EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6284  if (ExtVT != MVT::v2i32) {
6285  Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6286  Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6288  ExtVT.getVectorElementType(), 4)));
6289  Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6290  Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6291  DAG.getValueType(MVT::v2i32));
6292  }
6293 
6294  return Op;
6295  }
6296 
6297  return SDValue();
6298 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
EVT getVectorElementType() const
Definition: ValueTypes.h:217
const SDValue & getOperand(unsigned i) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue getValueType(EVT)
SDValue PPCTargetLowering::LowerSRA_PARTS ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5662 of file PPCISelLowering.cpp.

5662  {
5663  SDLoc dl(Op);
5664  EVT VT = Op.getValueType();
5665  unsigned BitWidth = VT.getSizeInBits();
5666  assert(Op.getNumOperands() == 3 &&
5667  VT == Op.getOperand(1).getValueType() &&
5668  "Unexpected SRA!");
5669 
5670  // Expand into a bunch of logical ops, followed by a select_cc.
5671  SDValue Lo = Op.getOperand(0);
5672  SDValue Hi = Op.getOperand(1);
5673  SDValue Amt = Op.getOperand(2);
5674  EVT AmtVT = Amt.getValueType();
5675 
5676  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5677  DAG.getConstant(BitWidth, AmtVT), Amt);
5678  SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5679  SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5680  SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5681  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5682  DAG.getConstant(-BitWidth, AmtVT));
5683  SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5684  SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5685  SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5686  Tmp4, Tmp6, ISD::SETLE);
5687  SDValue OutOps[] = { OutLo, OutHi };
5688  return DAG.getMergeValues(OutOps, dl);
5689 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
unsigned getNumOperands() const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue PPCTargetLowering::LowerSRL_PARTS ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5633 of file PPCISelLowering.cpp.

5633  {
5634  EVT VT = Op.getValueType();
5635  SDLoc dl(Op);
5636  unsigned BitWidth = VT.getSizeInBits();
5637  assert(Op.getNumOperands() == 3 &&
5638  VT == Op.getOperand(1).getValueType() &&
5639  "Unexpected SRL!");
5640 
5641  // Expand into a bunch of logical ops. Note that these ops
5642  // depend on the PPC behavior for oversized shift amounts.
5643  SDValue Lo = Op.getOperand(0);
5644  SDValue Hi = Op.getOperand(1);
5645  SDValue Amt = Op.getOperand(2);
5646  EVT AmtVT = Amt.getValueType();
5647 
5648  SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5649  DAG.getConstant(BitWidth, AmtVT), Amt);
5650  SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5651  SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5652  SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5653  SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5654  DAG.getConstant(-BitWidth, AmtVT));
5655  SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5656  SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5657  SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5658  SDValue OutOps[] = { OutLo, OutHi };
5659  return DAG.getMergeValues(OutOps, dl);
5660 }
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
unsigned getNumOperands() const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue PPCTargetLowering::LowerSTACKRESTORE ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
) const
private

Definition at line 5076 of file PPCISelLowering.cpp.

5077  {
5078  // When we pop the dynamic allocation we need to restore the SP link.
5079  SDLoc dl(Op);
5080 
5081  // Get the corect type for pointers.
5082  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5083 
5084  // Construct the stack pointer operand.
5085  bool isPPC64 = Subtarget.isPPC64();
5086  unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5087  SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5088 
5089  // Get the operands for the STACKRESTORE.
5090  SDValue Chain = Op.getOperand(0);
5091  SDValue SaveSP = Op.getOperand(1);
5092 
5093  // Load the old link SP.
5094  SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5096  false, false, false, 0);
5097 
5098  // Restore the stack pointer.
5099  Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5100 
5101  // Store the old link SP.
5102  return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5103  false, false, 0);
5104 }
SDValue getValue(unsigned R) const
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getOperand(unsigned i) const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getRegister(unsigned Reg, EVT VT)
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue PPCTargetLowering::LowerSTORE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5215 of file PPCISelLowering.cpp.

5215  {
5216  assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5217  "Custom lowering only for i1 stores");
5218 
5219  // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5220 
5221  SDLoc dl(Op);
5222  StoreSDNode *ST = cast<StoreSDNode>(Op);
5223 
5224  SDValue Chain = ST->getChain();
5225  SDValue BasePtr = ST->getBasePtr();
5226  SDValue Value = ST->getValue();
5227  MachineMemOperand *MMO = ST->getMemOperand();
5228 
5229  Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5230  return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5231 }
virtual MVT getPointerTy(uint32_t=0) const
const SDValue & getBasePtr() const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
const SDValue & getValue() const
const SDValue & getChain() const
MachineMemOperand * getMemOperand() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
LLVM Value Representation.
Definition: Value.h:69
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue PPCTargetLowering::LowerTRUNCATE ( SDValue  Op,
SelectionDAG DAG 
) const
private

Definition at line 5234 of file PPCISelLowering.cpp.

5234  {
5235  assert(Op.getValueType() == MVT::i1 &&
5236  "Custom lowering only for i1 results");
5237 
5238  SDLoc DL(Op);
5240  Op.getOperand(0));
5241 }
const DataLayout * DL
True if this is a little endian target.
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
SDValue PPCTargetLowering::LowerVAARG ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
) const
private

Definition at line 1842 of file PPCISelLowering.cpp.

1843  {
1844  SDNode *Node = Op.getNode();
1845  EVT VT = Node->getValueType(0);
1846  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1847  SDValue InChain = Node->getOperand(0);
1848  SDValue VAListPtr = Node->getOperand(1);
1849  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1850  SDLoc dl(Node);
1851 
1852  assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1853 
1854  // gpr_index
1855  SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1856  VAListPtr, MachinePointerInfo(SV), MVT::i8,
1857  false, false, 0);
1858  InChain = GprIndex.getValue(1);
1859 
1860  if (VT == MVT::i64) {
1861  // Check if GprIndex is even
1862  SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1863  DAG.getConstant(1, MVT::i32));
1864  SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1865  DAG.getConstant(0, MVT::i32), ISD::SETNE);
1866  SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1867  DAG.getConstant(1, MVT::i32));
1868  // Align GprIndex to be even if it isn't
1869  GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1870  GprIndex);
1871  }
1872 
1873  // fpr index is 1 byte after gpr
1874  SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1875  DAG.getConstant(1, MVT::i32));
1876 
1877  // fpr
1878  SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1879  FprPtr, MachinePointerInfo(SV), MVT::i8,
1880  false, false, 0);
1881  InChain = FprIndex.getValue(1);
1882 
1883  SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1884  DAG.getConstant(8, MVT::i32));
1885 
1886  SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1887  DAG.getConstant(4, MVT::i32));
1888 
1889  // areas
1890  SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1891  MachinePointerInfo(), false, false,
1892  false, 0);
1893  InChain = OverflowArea.getValue(1);
1894 
1895  SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1896  MachinePointerInfo(), false, false,
1897  false, 0);
1898  InChain = RegSaveArea.getValue(1);
1899 
1900  // select overflow_area if index > 8
1901  SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1902  DAG.getConstant(8, MVT::i32), ISD::SETLT);
1903 
1904  // adjustment constant gpr_index * 4/8
1905  SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1906  VT.isInteger() ? GprIndex : FprIndex,
1907  DAG.getConstant(VT.isInteger() ? 4 : 8,
1908  MVT::i32));
1909 
1910  // OurReg = RegSaveArea + RegConstant
1911  SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1912  RegConstant);
1913 
1914  // Floating types are 32 bytes into RegSaveArea
1915  if (VT.isFloatingPoint())
1916  OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1917  DAG.getConstant(32, MVT::i32));
1918 
1919  // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1920  SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1921  VT.isInteger() ? GprIndex : FprIndex,
1922  DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1923  MVT::i32));
1924 
1925  InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1926  VT.isInteger() ? VAListPtr : FprPtr,
1927  MachinePointerInfo(SV),
1928  MVT::i8, false, false, 0);
1929 
1930  // determine if we should load from reg_save_area or overflow_area
1931  SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1932 
1933  // increase overflow_area by 4/8 if gpr/fpr > 8
1934  SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1935  DAG.getConstant(VT.isInteger() ? 4 : 8,
1936  MVT::i32));
1937 
1938  OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1939  OverflowAreaPlusN);
1940 
1941  InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1942  OverflowAreaPtr,
1944  MVT::i32, false, false, 0);
1945 
1946  return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1947  false, false, false, 0);
1948 }
SDValue getValue(unsigned R) const
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
virtual MVT getPointerTy(uint32_t=0) const
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
const DomTreeNodeT * Node
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDNode * getNode() const
get the SDNode which holds the desired result
assert(Globals.size() > 1)
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
LLVM Value Representation.
Definition: Value.h:69
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue PPCTargetLowering::LowerVACOPY ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
) const
private

Definition at line 1950 of file PPCISelLowering.cpp.

1951  {
1952  assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1953 
1954  // We have to copy the entire va_list struct:
1955  // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1956  return DAG.getMemcpy(Op.getOperand(0), Op,
1957  Op.getOperand(1), Op.getOperand(2),
1958  DAG.getConstant(12, MVT::i32), 8, false, true,
1960 }
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue PPCTargetLowering::LowerVASTART ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
) const
private

Definition at line 2006 of file PPCISelLowering.cpp.

2007  {
2008  MachineFunction &MF = DAG.getMachineFunction();
2009  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2010 
2011  SDLoc dl(Op);
2012 
2013  if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2014  // vastart just stores the address of the VarArgsFrameIndex slot into the
2015  // memory location argument.
2016  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2017  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2018  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2019  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2020  MachinePointerInfo(SV),
2021  false, false, 0);
2022  }
2023 
2024  // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2025  // We suppose the given va_list is already allocated.
2026  //
2027  // typedef struct {
2028  // char gpr; /* index into the array of 8 GPRs
2029  // * stored in the register save area
2030  // * gpr=0 corresponds to r3,
2031  // * gpr=1 to r4, etc.
2032  // */
2033  // char fpr; /* index into the array of 8 FPRs
2034  // * stored in the register save area
2035  // * fpr=0 corresponds to f1,
2036  // * fpr=1 to f2, etc.
2037  // */
2038  // char *overflow_arg_area;
2039  // /* location on stack that holds
2040  // * the next overflow argument
2041  // */
2042  // char *reg_save_area;
2043  // /* where r3:r10 and f1:f8 (if saved)
2044  // * are stored
2045  // */
2046  // } va_list[1];
2047 
2048 
2049  SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2050  SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2051 
2052 
2053  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2054 
2055  SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2056  PtrVT);
2057  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2058  PtrVT);
2059 
2060  uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2061  SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2062 
2063  uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2064  SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2065 
2066  uint64_t FPROffset = 1;
2067  SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2068 
2069  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2070 
2071  // Store first byte : number of int regs
2072  SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2073  Op.getOperand(1),
2074  MachinePointerInfo(SV),
2075  MVT::i8, false, false, 0);
2076  uint64_t nextOffset = FPROffset;
2077  SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2078  ConstFPROffset);
2079 
2080  // Store second byte : number of float regs
2081  SDValue secondStore =
2082  DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2083  MachinePointerInfo(SV, nextOffset), MVT::i8,
2084  false, false, 0);
2085  nextOffset += StackOffset;
2086  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2087 
2088  // Store second word : arguments given on stack
2089  SDValue thirdStore =
2090  DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2091  MachinePointerInfo(SV, nextOffset),
2092  false, false, 0);
2093  nextOffset += FrameOffset;
2094  nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2095 
2096  // Store third word : arguments given in registers
2097  return DAG.getStore(thirdStore, dl, FR, nextPtr,
2098  MachinePointerInfo(SV, nextOffset),
2099  false, false, 0);
2100 
2101 }
bool isDarwinABI() const
Definition: PPCSubtarget.h:228
unsigned getVarArgsNumGPR() const
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
unsigned getVarArgsNumFPR() const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
bool isPPC64() const
Definition: PPCSubtarget.h:168
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM Value Representation.
Definition: Value.h:69
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG 
) const
private

LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this is a shuffle we can handle in a single instruction, return it. Otherwise, return the code it can be lowered into. Worst case, it can always be lowered into a vperm.

Definition at line 6027 of file PPCISelLowering.cpp.

6028  {
6029  SDLoc dl(Op);
6030  SDValue V1 = Op.getOperand(0);
6031  SDValue V2 = Op.getOperand(1);
6032  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6033  EVT VT = Op.getValueType();
6035 
6036  // Cases that are handled by instructions that take permute immediates
6037  // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6038  // selected by the instruction selector.
6039  if (V2.getOpcode() == ISD::UNDEF) {
6040  if (PPC::isSplatShuffleMask(SVOp, 1) ||
6041  PPC::isSplatShuffleMask(SVOp, 2) ||
6042  PPC::isSplatShuffleMask(SVOp, 4) ||
6043  PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6044  PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6045  PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6046  PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6047  PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6048  PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6049  PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6050  PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6051  PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6052  return Op;
6053  }
6054  }
6055 
6056  // Altivec has a variety of "shuffle immediates" that take two vector inputs
6057  // and produce a fixed permutation. If any of these match, do not lower to
6058  // VPERM.
6059  unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6060  if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6061  PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6062  PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6063  PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6064  PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6065  PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6066  PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6067  PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6068  PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6069  return Op;
6070 
6071  // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6072  // perfect shuffle table to emit an optimal matching sequence.
6073  ArrayRef<int> PermMask = SVOp->getMask();
6074 
6075  unsigned PFIndexes[4];
6076  bool isFourElementShuffle = true;
6077  for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6078  unsigned EltNo = 8; // Start out undef.
6079  for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6080  if (PermMask[i*4+j] < 0)
6081  continue; // Undef, ignore it.
6082 
6083  unsigned ByteSource = PermMask[i*4+j];
6084  if ((ByteSource & 3) != j) {
6085  isFourElementShuffle = false;
6086  break;
6087  }
6088 
6089  if (EltNo == 8) {
6090  EltNo = ByteSource/4;
6091  } else if (EltNo != ByteSource/4) {
6092  isFourElementShuffle = false;
6093  break;
6094  }
6095  }
6096  PFIndexes[i] = EltNo;
6097  }
6098 
6099  // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6100  // perfect shuffle vector to determine if it is cost effective to do this as
6101  // discrete instructions, or whether we should use a vperm.
6102  // For now, we skip this for little endian until such time as we have a
6103  // little-endian perfect shuffle table.
6104  if (isFourElementShuffle && !isLittleEndian) {
6105  // Compute the index in the perfect shuffle table.
6106  unsigned PFTableIndex =
6107  PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6108 
6109  unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6110  unsigned Cost = (PFEntry >> 30);
6111 
6112  // Determining when to avoid vperm is tricky. Many things affect the cost
6113  // of vperm, particularly how many times the perm mask needs to be computed.
6114  // For example, if the perm mask can be hoisted out of a loop or is already
6115  // used (perhaps because there are multiple permutes with the same shuffle
6116  // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6117  // the loop requires an extra register.
6118  //
6119  // As a compromise, we only emit discrete instructions if the shuffle can be
6120  // generated in 3 or fewer operations. When we have loop information
6121  // available, if this block is within a loop, we should avoid using vperm
6122  // for 3-operation perms and use a constant pool load instead.
6123  if (Cost < 3)
6124  return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6125  }
6126 
6127  // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6128  // vector that will get spilled to the constant pool.
6129  if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6130 
6131  // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6132  // that it is in input element units, not in bytes. Convert now.
6133 
6134  // For little endian, the order of the input vectors is reversed, and
6135  // the permutation mask is complemented with respect to 31. This is
6136  // necessary to produce proper semantics with the big-endian-biased vperm
6137  // instruction.
6138  EVT EltVT = V1.getValueType().getVectorElementType();
6139  unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6140 
6141  SmallVector<SDValue, 16> ResultMask;
6142  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6143  unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6144 
6145  for (unsigned j = 0; j != BytesPerElement; ++j)
6146  if (isLittleEndian)
6147  ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6148  MVT::i32));
6149  else
6150  ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6151  MVT::i32));
6152  }
6153 
6154  SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6155  ResultMask);
6156  if (isLittleEndian)
6157  return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6158  V2, V1, VPermMask);
6159  else
6160  return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6161  V1, V2, VPermMask);
6162 }
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
bool isLittleEndian() const
EVT getVectorElementType() const
Definition: ValueTypes.h:217
static const unsigned PerfectShuffleTable[6561+1]
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
const PPCSubtarget & Subtarget
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl)
const SDValue & getOperand(unsigned i) const
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
unsigned getOpcode() const
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
ArrayRef< int > getMask() const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
const char * TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
virtualinherited

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented in llvm::X86TargetLowering.

Definition at line 2091 of file TargetLowering.cpp.

2091  {
2092  if (ConstraintVT.isInteger())
2093  return "r";
2094  if (ConstraintVT.isFloatingPoint())
2095  return "f"; // works for many targets
2096  return nullptr;
2097 }
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
std::pair< SDValue, SDValue > TargetLowering::makeLibCall ( SelectionDAG DAG,
RTLIB::Libcall  LC,
EVT  RetVT,
const SDValue Ops,
unsigned  NumOps,
bool  isSigned,
SDLoc  dl,
bool  doesNotReturn = false,
bool  isReturnValueUsed = true 
) const
inherited

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

Definition at line 86 of file TargetLowering.cpp.

91  {
93  Args.reserve(NumOps);
94 
96  for (unsigned i = 0; i != NumOps; ++i) {
97  Entry.Node = Ops[i];
98  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99  Entry.isSExt = isSigned;
100  Entry.isZExt = !isSigned;
101  Args.push_back(Entry);
102  }
104 
105  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
107  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109  .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110  .setSExtResult(isSigned).setZExtResult(!isSigned);
111  return LowerCallTo(CLI);
112 }
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
SDValue getExternalSymbol(const char *Sym, EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
std::vector< ArgListEntry > ArgListTy
const char * Args[]
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EVT getValueType() const
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
virtual bool llvm::TargetLowering::mayBeEmittedAsTailCall ( CallInst ) const
inlinevirtualinherited

Return true if the target may be able emit the call instruction as a tail call. This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SystemZTargetLowering.

Definition at line 2304 of file TargetLowering.h.

2304  {
2305  return false;
2306  }
TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( ImmutableCallSite  CS) const
virtualinherited

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ConstraintOperands - Information about all of the constraints.

Definition at line 2233 of file TargetLowering.cpp.

2234  {
2235  /// ConstraintOperands - Information about all of the constraints.
2236  AsmOperandInfoVector ConstraintOperands;
2237  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2238  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2239 
2240  // Do a prepass over the constraints, canonicalizing them, and building up the
2241  // ConstraintOperands list.
2243  ConstraintInfos = IA->ParseConstraints();
2244 
2245  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2246  unsigned ResNo = 0; // ResNo - The result number of the next output.
2247 
2248  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2249  ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2250  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2251 
2252  // Update multiple alternative constraint count.
2253  if (OpInfo.multipleAlternatives.size() > maCount)
2254  maCount = OpInfo.multipleAlternatives.size();
2255 
2256  OpInfo.ConstraintVT = MVT::Other;
2257 
2258  // Compute the value type for each operand.
2259  switch (OpInfo.Type) {
2260  case InlineAsm::isOutput:
2261  // Indirect outputs just consume an argument.
2262  if (OpInfo.isIndirect) {
2263  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2264  break;
2265  }
2266 
2267  // The return value of the call is this value. As such, there is no
2268  // corresponding argument.
2269  assert(!CS.getType()->isVoidTy() &&
2270  "Bad inline asm!");
2271  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2272  OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2273  } else {
2274  assert(ResNo == 0 && "Asm only has one result!");
2275  OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2276  }
2277  ++ResNo;
2278  break;
2279  case InlineAsm::isInput:
2280  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2281  break;
2282  case InlineAsm::isClobber:
2283  // Nothing to do.
2284  break;
2285  }
2286 
2287  if (OpInfo.CallOperandVal) {
2288  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2289  if (OpInfo.isIndirect) {
2290  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2291  if (!PtrTy)
2292  report_fatal_error("Indirect operand for inline asm not a pointer!");
2293  OpTy = PtrTy->getElementType();
2294  }
2295 
2296  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2297  if (StructType *STy = dyn_cast<StructType>(OpTy))
2298  if (STy->getNumElements() == 1)
2299  OpTy = STy->getElementType(0);
2300 
2301  // If OpTy is not a single value, it may be a struct/union that we
2302  // can tile with integers.
2303  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2304  unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2305  switch (BitSize) {
2306  default: break;
2307  case 1:
2308  case 8:
2309  case 16:
2310  case 32:
2311  case 64:
2312  case 128:
2313  OpInfo.ConstraintVT =
2314  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2315  break;
2316  }
2317  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2318  unsigned PtrSize
2319  = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2320  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2321  } else {
2322  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2323  }
2324  }
2325  }
2326 
2327  // If we have multiple alternative constraints, select the best alternative.
2328  if (ConstraintInfos.size()) {
2329  if (maCount) {
2330  unsigned bestMAIndex = 0;
2331  int bestWeight = -1;
2332  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2333  int weight = -1;
2334  unsigned maIndex;
2335  // Compute the sums of the weights for each alternative, keeping track
2336  // of the best (highest weight) one so far.
2337  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2338  int weightSum = 0;
2339  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2340  cIndex != eIndex; ++cIndex) {
2341  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2342  if (OpInfo.Type == InlineAsm::isClobber)
2343  continue;
2344 
2345  // If this is an output operand with a matching input operand,
2346  // look up the matching input. If their types mismatch, e.g. one
2347  // is an integer, the other is floating point, or their sizes are
2348  // different, flag it as an maCantMatch.
2349  if (OpInfo.hasMatchingInput()) {
2350  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2351  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2352  if ((OpInfo.ConstraintVT.isInteger() !=
2353  Input.ConstraintVT.isInteger()) ||
2354  (OpInfo.ConstraintVT.getSizeInBits() !=
2355  Input.ConstraintVT.getSizeInBits())) {
2356  weightSum = -1; // Can't match.
2357  break;
2358  }
2359  }
2360  }
2361  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2362  if (weight == -1) {
2363  weightSum = -1;
2364  break;
2365  }
2366  weightSum += weight;
2367  }
2368  // Update best.
2369  if (weightSum > bestWeight) {
2370  bestWeight = weightSum;
2371  bestMAIndex = maIndex;
2372  }
2373  }
2374 
2375  // Now select chosen alternative in each constraint.
2376  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2377  cIndex != eIndex; ++cIndex) {
2378  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2379  if (cInfo.Type == InlineAsm::isClobber)
2380  continue;
2381  cInfo.selectAlternative(bestMAIndex);
2382  }
2383  }
2384  }
2385 
2386  // Check and hook up tied operands, choose constraint code to use.
2387  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2388  cIndex != eIndex; ++cIndex) {
2389  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2390 
2391  // If this is an output operand with a matching input operand, look up the
2392  // matching input. If their types mismatch, e.g. one is an integer, the
2393  // other is floating point, or their sizes are different, flag it as an
2394  // error.
2395  if (OpInfo.hasMatchingInput()) {
2396  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2397 
2398  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2399  std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2400  getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2401  OpInfo.ConstraintVT);
2402  std::pair<unsigned, const TargetRegisterClass*> InputRC =
2403  getRegForInlineAsmConstraint(Input.ConstraintCode,
2404  Input.ConstraintVT);
2405  if ((OpInfo.ConstraintVT.isInteger() !=
2406  Input.ConstraintVT.isInteger()) ||
2407  (MatchRC.second != InputRC.second)) {
2408  report_fatal_error("Unsupported asm: input constraint"
2409  " with a matching output constraint of"
2410  " incompatible type!");
2411  }
2412  }
2413 
2414  }
2415  }
2416 
2417  return ConstraintOperands;
2418 }
static MVT getIntegerVT(unsigned BitWidth)
Type * getType() const
Definition: CallSite.h:157
ValTy * getArgument(unsigned ArgNo) const
Definition: CallSite.h:113
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
bool isSingleValueType() const
Definition: Type.h:250
MVT getSimpleValueType(Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
ValTy * getCalledValue() const
Definition: CallSite.h:85
Type * getElementType() const
Definition: DerivedTypes.h:319
assert(Globals.size() > 1)
const DataLayout * getDataLayout() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
std::vector< AsmOperandInfo > AsmOperandInfoVector
static IntegerType * get(LLVMContext &C, unsigned NumBits)
Get or create an IntegerType instance.
Definition: Type.cpp:299
static cl::opt< std::string > Input(cl::Positional, cl::desc("<input>"), cl::init("-"))
bool isSized(SmallPtrSet< const Type *, 4 > *Visited=nullptr) const
Definition: Type.h:268
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
LLVM Value Representation.
Definition: Value.h:69
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
Definition: InlineAsm.cpp:203
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
SDValue PPCTargetLowering::PerformDAGCombine ( SDNode N,
DAGCombinerInfo DCI 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 8176 of file PPCISelLowering.cpp.

8177  {
8178  const TargetMachine &TM = getTargetMachine();
8179  SelectionDAG &DAG = DCI.DAG;
8180  SDLoc dl(N);
8181  switch (N->getOpcode()) {
8182  default: break;
8183  case PPCISD::SHL:
8184  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8185  if (C->isNullValue()) // 0 << V -> 0.
8186  return N->getOperand(0);
8187  }
8188  break;
8189  case PPCISD::SRL:
8190  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8191  if (C->isNullValue()) // 0 >>u V -> 0.
8192  return N->getOperand(0);
8193  }
8194  break;
8195  case PPCISD::SRA:
8196  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8197  if (C->isNullValue() || // 0 >>s V -> 0.
8198  C->isAllOnesValue()) // -1 >>s V -> -1.
8199  return N->getOperand(0);
8200  }
8201  break;
8202  case ISD::SIGN_EXTEND:
8203  case ISD::ZERO_EXTEND:
8204  case ISD::ANY_EXTEND:
8205  return DAGCombineExtBoolTrunc(N, DCI);
8206  case ISD::TRUNCATE:
8207  case ISD::SETCC:
8208  case ISD::SELECT_CC:
8209  return DAGCombineTruncBoolExt(N, DCI);
8210  case ISD::FDIV: {
8212  "Reciprocal estimates require UnsafeFPMath");
8213 
8214  if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8215  SDValue RV =
8217  if (RV.getNode()) {
8218  DCI.AddToWorklist(RV.getNode());
8219  return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8220  N->getOperand(0), RV);
8221  }
8222  } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8223  N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8224  SDValue RV =
8226  DCI);
8227  if (RV.getNode()) {
8228  DCI.AddToWorklist(RV.getNode());
8229  RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8230  N->getValueType(0), RV);
8231  DCI.AddToWorklist(RV.getNode());
8232  return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8233  N->getOperand(0), RV);
8234  }
8235  } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8236  N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8237  SDValue RV =
8239  DCI);
8240  if (RV.getNode()) {
8241  DCI.AddToWorklist(RV.getNode());
8242  RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8243  N->getValueType(0), RV,
8244  N->getOperand(1).getOperand(1));
8245  DCI.AddToWorklist(RV.getNode());
8246  return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8247  N->getOperand(0), RV);
8248  }
8249  }
8250 
8251  SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8252  if (RV.getNode()) {
8253  DCI.AddToWorklist(RV.getNode());
8254  return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8255  N->getOperand(0), RV);
8256  }
8257 
8258  }
8259  break;
8260  case ISD::FSQRT: {
8262  "Reciprocal estimates require UnsafeFPMath");
8263 
8264  // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8265  // reciprocal sqrt.
8266  SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8267  if (RV.getNode()) {
8268  DCI.AddToWorklist(RV.getNode());
8269  RV = DAGCombineFastRecip(RV, DCI);
8270  if (RV.getNode()) {
8271  // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8272  // this case and force the answer to 0.
8273 
8274  EVT VT = RV.getValueType();
8275 
8276  SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8277  if (VT.isVector()) {
8278  assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8279  Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8280  }
8281 
8282  SDValue ZeroCmp =
8283  DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8284  N->getOperand(0), Zero, ISD::SETEQ);
8285  DCI.AddToWorklist(ZeroCmp.getNode());
8286  DCI.AddToWorklist(RV.getNode());
8287 
8288  RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8289  ZeroCmp, Zero, RV);
8290  return RV;
8291  }
8292  }
8293 
8294  }
8295  break;
8296  case ISD::SINT_TO_FP:
8298  if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8299  // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8300  // We allow the src/dst to be either f32/f64, but the intermediate
8301  // type must be i64.
8302  if (N->getOperand(0).getValueType() == MVT::i64 &&
8304  SDValue Val = N->getOperand(0).getOperand(0);
8305  if (Val.getValueType() == MVT::f32) {
8306  Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8307  DCI.AddToWorklist(Val.getNode());
8308  }
8309 
8310  Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8311  DCI.AddToWorklist(Val.getNode());
8312  Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8313  DCI.AddToWorklist(Val.getNode());
8314  if (N->getValueType(0) == MVT::f32) {
8315  Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8316  DAG.getIntPtrConstant(0));
8317  DCI.AddToWorklist(Val.getNode());
8318  }
8319  return Val;
8320  } else if (N->getOperand(0).getValueType() == MVT::i32) {
8321  // If the intermediate type is i32, we can avoid the load/store here
8322  // too.
8323  }
8324  }
8325  }
8326  break;
8327  case ISD::STORE:
8328  // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8329  if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8330  !cast<StoreSDNode>(N)->isTruncatingStore() &&
8331  N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8332  N->getOperand(1).getValueType() == MVT::i32 &&
8334  SDValue Val = N->getOperand(1).getOperand(0);
8335  if (Val.getValueType() == MVT::f32) {
8336  Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8337  DCI.AddToWorklist(Val.getNode());
8338  }
8339  Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8340  DCI.AddToWorklist(Val.getNode());
8341 
8342  SDValue Ops[] = {
8343  N->getOperand(0), Val, N->getOperand(2),
8344  DAG.getValueType(N->getOperand(1).getValueType())
8345  };
8346 
8347  Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8348  DAG.getVTList(MVT::Other), Ops,
8349  cast<StoreSDNode>(N)->getMemoryVT(),
8350  cast<StoreSDNode>(N)->getMemOperand());
8351  DCI.AddToWorklist(Val.getNode());
8352  return Val;
8353  }
8354 
8355  // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8356  if (cast<StoreSDNode>(N)->isUnindexed() &&
8357  N->getOperand(1).getOpcode() == ISD::BSWAP &&
8358  N->getOperand(1).getNode()->hasOneUse() &&
8359  (N->getOperand(1).getValueType() == MVT::i32 ||
8360  N->getOperand(1).getValueType() == MVT::i16 ||
8361  (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8362  TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8363  N->getOperand(1).getValueType() == MVT::i64))) {
8364  SDValue BSwapOp = N->getOperand(1).getOperand(0);
8365  // Do an any-extend to 32-bits if this is a half-word input.
8366  if (BSwapOp.getValueType() == MVT::i16)
8367  BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8368 
8369  SDValue Ops[] = {
8370  N->getOperand(0), BSwapOp, N->getOperand(2),
8371  DAG.getValueType(N->getOperand(1).getValueType())
8372  };
8373  return
8375  Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8376  cast<StoreSDNode>(N)->getMemOperand());
8377  }
8378  break;
8379  case ISD::LOAD: {
8380  LoadSDNode *LD = cast<LoadSDNode>(N);
8381  EVT VT = LD->getValueType(0);
8382  Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8383  unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8384  if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8385  TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8386  (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8387  VT == MVT::v4i32 || VT == MVT::v4f32) &&
8388  LD->getAlignment() < ABIAlignment) {
8389  // This is a type-legal unaligned Altivec load.
8390  SDValue Chain = LD->getChain();
8391  SDValue Ptr = LD->getBasePtr();
8393 
8394  // This implements the loading of unaligned vectors as described in
8395  // the venerable Apple Velocity Engine overview. Specifically:
8396  // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8397  // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8398  //
8399  // The general idea is to expand a sequence of one or more unaligned
8400  // loads into an alignment-based permutation-control instruction (lvsl
8401  // or lvsr), a series of regular vector loads (which always truncate
8402  // their input address to an aligned address), and a series of
8403  // permutations. The results of these permutations are the requested
8404  // loaded values. The trick is that the last "extra" load is not taken
8405  // from the address you might suspect (sizeof(vector) bytes after the
8406  // last requested load), but rather sizeof(vector) - 1 bytes after the
8407  // last requested vector. The point of this is to avoid a page fault if
8408  // the base address happened to be aligned. This works because if the
8409  // base address is aligned, then adding less than a full vector length
8410  // will cause the last vector in the sequence to be (re)loaded.
8411  // Otherwise, the next vector will be fetched as you might suspect was
8412  // necessary.
8413 
8414  // We might be able to reuse the permutation generation from
8415  // a different base address offset from this one by an aligned amount.
8416  // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8417  // optimization later.
8418  Intrinsic::ID Intr = (isLittleEndian ?
8419  Intrinsic::ppc_altivec_lvsr :
8420  Intrinsic::ppc_altivec_lvsl);
8421  SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8422 
8423  // Refine the alignment of the original load (a "new" load created here
8424  // which was identical to the first except for the alignment would be
8425  // merged with the existing node regardless).
8426  MachineFunction &MF = DAG.getMachineFunction();
8427  MachineMemOperand *MMO =
8429  LD->getMemOperand()->getFlags(),
8430  LD->getMemoryVT().getStoreSize(),
8431  ABIAlignment);
8432  LD->refineAlignment(MMO);
8433  SDValue BaseLoad = SDValue(LD, 0);
8434 
8435  // Note that the value of IncOffset (which is provided to the next
8436  // load's pointer info offset value, and thus used to calculate the
8437  // alignment), and the value of IncValue (which is actually used to
8438  // increment the pointer value) are different! This is because we
8439  // require the next load to appear to be aligned, even though it
8440  // is actually offset from the base pointer by a lesser amount.
8441  int IncOffset = VT.getSizeInBits() / 8;
8442  int IncValue = IncOffset;
8443 
8444  // Walk (both up and down) the chain looking for another load at the real
8445  // (aligned) offset (the alignment of the other load does not matter in
8446  // this case). If found, then do not use the offset reduction trick, as
8447  // that will prevent the loads from being later combined (as they would
8448  // otherwise be duplicates).
8449  if (!findConsecutiveLoad(LD, DAG))
8450  --IncValue;
8451 
8452  SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8453  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8454 
8455  SDValue ExtraLoad =
8456  DAG.getLoad(VT, dl, Chain, Ptr,
8457  LD->getPointerInfo().getWithOffset(IncOffset),
8458  LD->isVolatile(), LD->isNonTemporal(),
8459  LD->isInvariant(), ABIAlignment);
8460 
8462  BaseLoad.getValue(1), ExtraLoad.getValue(1));
8463 
8464  if (BaseLoad.getValueType() != MVT::v4i32)
8465  BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8466 
8467  if (ExtraLoad.getValueType() != MVT::v4i32)
8468  ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8469 
8470  // Because vperm has a big-endian bias, we must reverse the order
8471  // of the input vectors and complement the permute control vector
8472  // when generating little endian code. We have already handled the
8473  // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8474  // and ExtraLoad here.
8475  SDValue Perm;
8476  if (isLittleEndian)
8477  Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8478  ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8479  else
8480  Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8481  BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8482 
8483  if (VT != MVT::v4i32)
8484  Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8485 
8486  // Now we need to be really careful about how we update the users of the
8487  // original load. We cannot just call DCI.CombineTo (or
8488  // DAG.ReplaceAllUsesWith for that matter), because the load still has
8489  // uses created here (the permutation for example) that need to stay.
8490  SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8491  while (UI != UE) {
8492  SDUse &Use = UI.getUse();
8493  SDNode *User = *UI;
8494  // Note: BaseLoad is checked here because it might not be N, but a
8495  // bitcast of N.
8496  if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8497  User == TF.getNode() || Use.getResNo() > 1) {
8498  ++UI;
8499  continue;
8500  }
8501 
8502  SDValue To = Use.getResNo() ? TF : Perm;
8503  ++UI;
8504 
8506  for (const SDUse &O : User->ops()) {
8507  if (O == Use)
8508  Ops.push_back(To);
8509  else
8510  Ops.push_back(O);
8511  }
8512 
8513  DAG.UpdateNodeOperands(User, Ops);
8514  }
8515 
8516  return SDValue(N, 0);
8517  }
8518  }
8519  break;
8520  case ISD::INTRINSIC_WO_CHAIN: {
8521  bool isLittleEndian = Subtarget.isLittleEndian();
8522  Intrinsic::ID Intr = (isLittleEndian ?
8523  Intrinsic::ppc_altivec_lvsr :
8524  Intrinsic::ppc_altivec_lvsl);
8525  if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8526  N->getOperand(1)->getOpcode() == ISD::ADD) {
8527  SDValue Add = N->getOperand(1);
8528 
8529  if (DAG.MaskedValueIsZero(Add->getOperand(1),
8530  APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8532  SDNode *BasePtr = Add->getOperand(0).getNode();
8533  for (SDNode::use_iterator UI = BasePtr->use_begin(),
8534  UE = BasePtr->use_end(); UI != UE; ++UI) {
8535  if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8536  cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8537  Intr) {
8538  // We've found another LVSL/LVSR, and this address is an aligned
8539  // multiple of that one. The results will be the same, so use the
8540  // one we've just found instead.
8541 
8542  return SDValue(*UI, 0);
8543  }
8544  }
8545  }
8546  }
8547  }
8548 
8549  break;
8550  case ISD::BSWAP:
8551  // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8552  if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8553  N->getOperand(0).hasOneUse() &&
8554  (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8555  (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8556  TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8557  N->getValueType(0) == MVT::i64))) {
8558  SDValue Load = N->getOperand(0);
8559  LoadSDNode *LD = cast<LoadSDNode>(Load);
8560  // Create the byte-swapping load.
8561  SDValue Ops[] = {
8562  LD->getChain(), // Chain
8563  LD->getBasePtr(), // Ptr
8564  DAG.getValueType(N->getValueType(0)) // VT
8565  };
8566  SDValue BSLoad =
8568  DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8570  Ops, LD->getMemoryVT(), LD->getMemOperand());
8571 
8572  // If this is an i16 load, insert the truncate.
8573  SDValue ResVal = BSLoad;
8574  if (N->getValueType(0) == MVT::i16)
8575  ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8576 
8577  // First, combine the bswap away. This makes the value produced by the
8578  // load dead.
8579  DCI.CombineTo(N, ResVal);
8580 
8581  // Next, combine the load away, we give it a bogus result value but a real
8582  // chain result. The result value is dead because the bswap is dead.
8583  DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8584 
8585  // Return N so it doesn't get rechecked!
8586  return SDValue(N, 0);
8587  }
8588 
8589  break;
8590  case PPCISD::VCMP: {
8591  // If a VCMPo node already exists with exactly the same operands as this
8592  // node, use its result instead of this node (VCMPo computes both a CR6 and
8593  // a normal output).
8594  //
8595  if (!N->getOperand(0).hasOneUse() &&
8596  !N->getOperand(1).hasOneUse() &&
8597  !N->getOperand(2).hasOneUse()) {
8598 
8599  // Scan all of the users of the LHS, looking for VCMPo's that match.
8600  SDNode *VCMPoNode = nullptr;
8601 
8602  SDNode *LHSN = N->getOperand(0).getNode();
8603  for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8604  UI != E; ++UI)
8605  if (UI->getOpcode() == PPCISD::VCMPo &&
8606  UI->getOperand(1) == N->getOperand(1) &&
8607  UI->getOperand(2) == N->getOperand(2) &&
8608  UI->getOperand(0) == N->getOperand(0)) {
8609  VCMPoNode = *UI;
8610  break;
8611  }
8612 
8613  // If there is no VCMPo node, or if the flag value has a single use, don't
8614  // transform this.
8615  if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8616  break;
8617 
8618  // Look at the (necessarily single) use of the flag value. If it has a
8619  // chain, this transformation is more complex. Note that multiple things
8620  // could use the value result, which we should ignore.
8621  SDNode *FlagUser = nullptr;
8622  for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8623  FlagUser == nullptr; ++UI) {
8624  assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8625  SDNode *User = *UI;
8626  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8627  if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8628  FlagUser = User;
8629  break;
8630  }
8631  }
8632  }
8633 
8634  // If the user is a MFOCRF instruction, we know this is safe.
8635  // Otherwise we give up for right now.
8636  if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8637  return SDValue(VCMPoNode, 0);
8638  }
8639  break;
8640  }
8641  case ISD::BRCOND: {
8642  SDValue Cond = N->getOperand(1);
8643  SDValue Target = N->getOperand(2);
8644 
8645  if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8646  cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8647  Intrinsic::ppc_is_decremented_ctr_nonzero) {
8648 
8649  // We now need to make the intrinsic dead (it cannot be instruction
8650  // selected).
8651  DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8652  assert(Cond.getNode()->hasOneUse() &&
8653  "Counter decrement has more than one use");
8654 
8655  return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8656  N->getOperand(0), Target);
8657  }
8658  }
8659  break;
8660  case ISD::BR_CC: {
8661  // If this is a branch on an altivec predicate comparison, lower this so
8662  // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8663  // lowering is done pre-legalize, because the legalizer lowers the predicate
8664  // compare down to code that is difficult to reassemble.
8665  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8666  SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8667 
8668  // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8669  // value. If so, pass-through the AND to get to the intrinsic.
8670  if (LHS.getOpcode() == ISD::AND &&
8672  cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8673  Intrinsic::ppc_is_decremented_ctr_nonzero &&
8674  isa<ConstantSDNode>(LHS.getOperand(1)) &&
8675  !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8676  isZero())
8677  LHS = LHS.getOperand(0);
8678 
8679  if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8680  cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8681  Intrinsic::ppc_is_decremented_ctr_nonzero &&
8682  isa<ConstantSDNode>(RHS)) {
8683  assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8684  "Counter decrement comparison is not EQ or NE");
8685 
8686  unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8687  bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8688  (CC == ISD::SETNE && !Val);
8689 
8690  // We now need to make the intrinsic dead (it cannot be instruction
8691  // selected).
8692  DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8693  assert(LHS.getNode()->hasOneUse() &&
8694  "Counter decrement has more than one use");
8695 
8696  return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8697  N->getOperand(0), N->getOperand(4));
8698  }
8699 
8700  int CompareOpc;
8701  bool isDot;
8702 
8703  if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8704  isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8705  getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8706  assert(isDot && "Can't compare against a vector result!");
8707 
8708  // If this is a comparison against something other than 0/1, then we know
8709  // that the condition is never/always true.
8710  unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8711  if (Val != 0 && Val != 1) {
8712  if (CC == ISD::SETEQ) // Cond never true, remove branch.
8713  return N->getOperand(0);
8714  // Always !=, turn it into an unconditional branch.
8715  return DAG.getNode(ISD::BR, dl, MVT::Other,
8716  N->getOperand(0), N->getOperand(4));
8717  }
8718 
8719  bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8720 
8721  // Create the PPCISD altivec 'dot' comparison node.
8722  SDValue Ops[] = {
8723  LHS.getOperand(2), // LHS of compare
8724  LHS.getOperand(3), // RHS of compare
8725  DAG.getConstant(CompareOpc, MVT::i32)
8726  };
8727  EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8728  SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8729 
8730  // Unpack the result based on how the target uses it.
8731  PPC::Predicate CompOpc;
8732  switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8733  default: // Can't happen, don't crash on invalid number though.
8734  case 0: // Branch on the value of the EQ bit of CR6.
8735  CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8736  break;
8737  case 1: // Branch on the inverted value of the EQ bit of CR6.
8738  CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8739  break;
8740  case 2: // Branch on the value of the LT bit of CR6.
8741  CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8742  break;
8743  case 3: // Branch on the inverted value of the LT bit of CR6.
8744  CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8745  break;
8746  }
8747 
8748  return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8749  DAG.getConstant(CompOpc, MVT::i32),
8750  DAG.getRegister(PPC::CR6, MVT::i32),
8751  N->getOperand(4), CompNode.getValue(1));
8752  }
8753  break;
8754  }
8755  }
8756 
8757  return SDValue();
8758 }
static bool isZero(Value *V, const DataLayout *DL)
Definition: Lint.cpp:507
SDValue getValue(unsigned R) const
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
bool hasOneUse() const
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
bool isLittleEndian() const
Definition: PPCSubtarget.h:193
bool hasOneUse() const
const TargetMachine & getTargetMachine() const
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, SDLoc dl, EVT DestVT=MVT::Other)
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
const TargetMachine & TM
True if this is a little endian target.
static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG)
unsigned getOpcode() const
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
const SDValue & getOperand(unsigned Num) const
const SDValue & getBasePtr() const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
bool isLittleEndian() const
EVT getValueType(unsigned ResNo) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:69
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
Definition: ValueTypes.h:211
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
const PPCSubtarget & Subtarget
SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot)
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getStoreSize() const
Definition: ValueTypes.h:246
unsigned int getFlags() const
getFlags - Return the raw flags of the source value,
assert(Globals.size() > 1)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:511
const SDValue & getOperand(unsigned i) const
bool isNonTemporal() const
const DataLayout * getDataLayout() const
unsigned getOpcode() const
bool has64BitSupport() const
Definition: PPCSubtarget.h:172
use_iterator use_begin() const
bool isVolatile() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
const MachinePointerInfo & getPointerInfo() const
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
const STC & getSubtarget() const
bool isInvariant() const
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
const SDValue & getChain() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:314
MachineMemOperand * getMemOperand() const
SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
bool hasSTFIWX() const
Definition: PPCSubtarget.h:203
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
#define N
ArrayRef< SDUse > ops() const
bool isNON_EXTLoad(const SDNode *N)
EVT getValueType() const
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getValueType(EVT)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:984
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
unsigned getAlignment() const
SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const
unsigned getResNo() const
getResNo - Convenience function for get().getResNo().
SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const
void refineAlignment(const MachineMemOperand *NewMMO)
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad ( SDValue  Chain,
SDLoc  DL,
SelectionDAG DAG 
) const
inlinevirtualinherited

This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 2355 of file TargetLowering.h.

2356  {
2357  return Chain;
2358  }
void PPCTargetLowering::ReplaceNodeResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
) const
overridevirtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 6451 of file PPCISelLowering.cpp.

6453  {
6454  const TargetMachine &TM = getTargetMachine();
6455  SDLoc dl(N);
6456  switch (N->getOpcode()) {
6457  default:
6458  llvm_unreachable("Do not know how to custom type legalize this operation!");
6459  case ISD::INTRINSIC_W_CHAIN: {
6460  if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6461  Intrinsic::ppc_is_decremented_ctr_nonzero)
6462  break;
6463 
6464  assert(N->getValueType(0) == MVT::i1 &&
6465  "Unexpected result type for CTR decrement intrinsic");
6466  EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6467  SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6468  SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6469  N->getOperand(1));
6470 
6471  Results.push_back(NewInt);
6472  Results.push_back(NewInt.getValue(1));
6473  break;
6474  }
6475  case ISD::VAARG: {
6476  if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6477  || TM.getSubtarget<PPCSubtarget>().isPPC64())
6478  return;
6479 
6480  EVT VT = N->getValueType(0);
6481 
6482  if (VT == MVT::i64) {
6483  SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6484 
6485  Results.push_back(NewNode);
6486  Results.push_back(NewNode.getValue(1));
6487  }
6488  return;
6489  }
6490  case ISD::FP_ROUND_INREG: {
6491  assert(N->getValueType(0) == MVT::ppcf128);
6494  MVT::f64, N->getOperand(0),
6495  DAG.getIntPtrConstant(0));
6497  MVT::f64, N->getOperand(0),
6498  DAG.getIntPtrConstant(1));
6499 
6500  // Add the two halves of the long double in round-to-zero mode.
6501  SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6502 
6503  // We know the low half is about to be thrown away, so just use something
6504  // convenient.
6505  Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6506  FPreg, FPreg));
6507  return;
6508  }
6509  case ISD::FP_TO_SINT:
6510  // LowerFP_TO_INT() can only handle f32 and f64.
6511  if (N->getOperand(0).getValueType() == MVT::ppcf128)
6512  return;
6513  Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6514  return;
6515  }
6516 }
SDValue getValue(unsigned R) const
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
const TargetMachine & getTargetMachine() const
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
const TargetMachine & TM
True if this is a little endian target.
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
SDVTList getVTList(EVT VT)
const PPCSubtarget & Subtarget
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const
assert(Globals.size() > 1)
bool isSVR4ABI() const
Definition: PPCSubtarget.h:229
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const
const STC & getSubtarget() const
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
EVT getValueType() const
virtual void llvm::TargetLoweringBase::resetOperationActions ( )
inlinevirtualinherited

Reset the operation actions based on target options.

Reimplemented in llvm::X86TargetLowering.

Definition at line 959 of file TargetLowering.h.

959 {}
bool PPCTargetLowering::SelectAddressRegImm ( SDValue  N,
SDValue Disp,
SDValue Base,
SelectionDAG DAG,
bool  Aligned 
) const

SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg. If Aligned is true, only accept displacements suitable for STD and friends, i.e. multiples of 4.

Returns true if the address N can be represented by a base register plus a signed 16-bit displacement [r+imm], and if it is not better represented as reg+reg. If Aligned is true, only accept displacements suitable for STD and friends, i.e. multiples of 4.

Definition at line 1316 of file PPCISelLowering.cpp.

1319  {
1320  // FIXME dl should come from parent load or store, not from address
1321  SDLoc dl(N);
1322  // If this can be more profitably realized as r+r, fail.
1323  if (SelectAddressRegReg(N, Disp, Base, DAG))
1324  return false;
1325 
1326  if (N.getOpcode() == ISD::ADD) {
1327  short imm = 0;
1328  if (isIntS16Immediate(N.getOperand(1), imm) &&
1329  (!Aligned || (imm & 3) == 0)) {
1330  Disp = DAG.getTargetConstant(imm, N.getValueType());
1331  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1332  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1333  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1334  } else {
1335  Base = N.getOperand(0);
1336  }
1337  return true; // [r+i]
1338  } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1339  // Match LOAD (ADD (X, Lo(G))).
1340  assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1341  && "Cannot handle constant offsets yet!");
1342  Disp = N.getOperand(1).getOperand(0); // The global address.
1343  assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1344  Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1345  Disp.getOpcode() == ISD::TargetConstantPool ||
1346  Disp.getOpcode() == ISD::TargetJumpTable);
1347  Base = N.getOperand(0);
1348  return true; // [&g+r]
1349  }
1350  } else if (N.getOpcode() == ISD::OR) {
1351  short imm = 0;
1352  if (isIntS16Immediate(N.getOperand(1), imm) &&
1353  (!Aligned || (imm & 3) == 0)) {
1354  // If this is an or of disjoint bitfields, we can codegen this as an add
1355  // (for better address arithmetic) if the LHS and RHS of the OR are
1356  // provably disjoint.
1357  APInt LHSKnownZero, LHSKnownOne;
1358  DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1359 
1360  if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1361  // If all of the bits are known zero on the LHS or RHS, the add won't
1362  // carry.
1363  if (FrameIndexSDNode *FI =
1364  dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1365  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1366  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1367  } else {
1368  Base = N.getOperand(0);
1369  }
1370  Disp = DAG.getTargetConstant(imm, N.getValueType());
1371  return true;
1372  }
1373  }
1374  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1375  // Loading from a constant address.
1376 
1377  // If this address fits entirely in a 16-bit sext immediate field, codegen
1378  // this as "d, 0"
1379  short Imm;
1380  if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1381  Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1382  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1383  CN->getValueType(0));
1384  return true;
1385  }
1386 
1387  // Handle 32-bit sext immediates with LIS + addr mode.
1388  if ((CN->getValueType(0) == MVT::i32 ||
1389  (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1390  (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1391  int Addr = (int)CN->getZExtValue();
1392 
1393  // Otherwise, break this down into an LIS + disp.
1394  Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1395 
1396  Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1397  unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1398  Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1399  return true;
1400  }
1401  }
1402 
1403  Disp = DAG.getTargetConstant(0, getPointerTy());
1404  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1405  Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1406  fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1407  } else
1408  Base = N;
1409  return true; // [r+0]
1410 }
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1302
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
EVT getValueType(unsigned ResNo) const
virtual MVT getPointerTy(uint32_t=0) const
static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT)
const PPCSubtarget & Subtarget
SDValue getTargetFrameIndex(int FI, EVT VT)
Definition: SelectionDAG.h:439
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static bool isIntS16Immediate(SDNode *N, short &Imm)
unsigned getOpcode() const
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
bool isPPC64() const
Definition: PPCSubtarget.h:168
Class for arbitrary precision integers.
Definition: APInt.h:75
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
#define N
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
EVT getValueType() const
SDValue getRegister(unsigned Reg, EVT VT)
bool PPCTargetLowering::SelectAddressRegReg ( SDValue  N,
SDValue Base,
SDValue Index,
SelectionDAG DAG 
) const

SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an indexed [r+r] operation. Returns false if it can be more efficiently represented with [r+imm].

Definition at line 1231 of file PPCISelLowering.cpp.

1233  {
1234  short imm = 0;
1235  if (N.getOpcode() == ISD::ADD) {
1236  if (isIntS16Immediate(N.getOperand(1), imm))
1237  return false; // r+i
1238  if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1239  return false; // r+i
1240 
1241  Base = N.getOperand(0);
1242  Index = N.getOperand(1);
1243  return true;
1244  } else if (N.getOpcode() == ISD::OR) {
1245  if (isIntS16Immediate(N.getOperand(1), imm))
1246  return false; // r+i can fold it if we can.
1247 
1248  // If this is an or of disjoint bitfields, we can codegen this as an add
1249  // (for better address arithmetic) if the LHS and RHS of the OR are provably
1250  // disjoint.
1251  APInt LHSKnownZero, LHSKnownOne;
1252  APInt RHSKnownZero, RHSKnownOne;
1253  DAG.computeKnownBits(N.getOperand(0),
1254  LHSKnownZero, LHSKnownOne);
1255 
1256  if (LHSKnownZero.getBoolValue()) {
1257  DAG.computeKnownBits(N.getOperand(1),
1258  RHSKnownZero, RHSKnownOne);
1259  // If all of the bits are known zero on the LHS or RHS, the add won't
1260  // carry.
1261  if (~(LHSKnownZero | RHSKnownZero) == 0) {
1262  Base = N.getOperand(0);
1263  Index = N.getOperand(1);
1264  return true;
1265  }
1266  }
1267  }
1268 
1269  return false;
1270 }
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
bool getBoolValue() const
Convert APInt to a boolean value.
Definition: APInt.h:402
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
static bool isIntS16Immediate(SDNode *N, short &Imm)
unsigned getOpcode() const
Class for arbitrary precision integers.
Definition: APInt.h:75
bool PPCTargetLowering::SelectAddressRegRegOnly ( SDValue  N,
SDValue Base,
SDValue Index,
SelectionDAG DAG 
) const

SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+r] operation.

Definition at line 1414 of file PPCISelLowering.cpp.

1416  {
1417  // Check to see if we can easily represent this as an [r+r] address. This
1418  // will fail if it thinks that the address is more profitably represented as
1419  // reg+imm, e.g. where imm = 0.
1420  if (SelectAddressRegReg(N, Base, Index, DAG))
1421  return true;
1422 
1423  // If the operand is an addition, always emit this as [r+r], since this is
1424  // better (for code size, and execution, as the memop does the add for free)
1425  // than emitting an explicit add.
1426  if (N.getOpcode() == ISD::ADD) {
1427  Base = N.getOperand(0);
1428  Index = N.getOperand(1);
1429  return true;
1430  }
1431 
1432  // Otherwise, do it the hard way, using R0 as the base register.
1433  Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1434  N.getValueType());
1435  Index = N;
1436  return true;
1437 }
const PPCSubtarget & Subtarget
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
bool isPPC64() const
Definition: PPCSubtarget.h:168
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
#define N
EVT getValueType() const
SDValue getRegister(unsigned Reg, EVT VT)
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 964 of file TargetLowering.h.

964  {
965  BooleanContents = Ty;
967  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 971 of file TargetLowering.h.

971  {
972  BooleanContents = IntTy;
973  BooleanFloatContents = FloatTy;
974  }
BooleanContent BooleanFloatContents
BooleanContent BooleanContents
void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.

Definition at line 978 of file TargetLowering.h.

978  {
980  }
BooleanContent BooleanVectorContents
void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inlineinherited

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 1431 of file TargetLowering.h.

1431  {
1432  CmpLibcallCCs[Call] = CC;
1433  }
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1156 of file TargetLowering.h.

1157  {
1158  assert(VT < MVT::LAST_VALUETYPE &&
1159  (unsigned)CC < array_lengthof(CondCodeActions) &&
1160  "Table isn't big enough!");
1161  /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1162  /// value and the upper 27 bits index into the second dimension of the array
1163  /// to select what 32-bit value to use.
1164  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1165  CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1166  CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1167  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
void llvm::TargetLoweringBase::setExceptionPointerRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception address on entry to a landing pad.

Definition at line 1018 of file TargetLowering.h.

1018  {
1020  }
void llvm::TargetLoweringBase::setExceptionSelectorRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad.

Definition at line 1024 of file TargetLowering.h.

1024  {
1026  }
void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotectedinherited

Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1047 of file TargetLowering.h.

1047  {
1048  HasExtractBitsInsn = hasExtractInsn;
1049  }
void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotectedinherited

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1039 of file TargetLowering.h.

1039  {
1040  HasMultipleConditionRegisters = hasManyRegs;
1041  }
void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Definition at line 1131 of file TargetLowering.h.

1132  {
1134  (unsigned)Action < 0xf && "Table isn't big enough!");
1135  // Load action are kept in the upper half.
1136  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1137  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1138  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1145 of file TargetLowering.h.

1146  {
1148  (unsigned)Action < 0xf && "Table isn't big enough!");
1149  // Store action are kept in the lower half.
1150  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1151  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1152  }
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setInsertFencesForAtomic ( bool  fence)
inlineprotectedinherited

Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic.

Definition at line 1222 of file TargetLowering.h.

1222  {
1223  InsertFencesForAtomic = fence;
1224  }
void llvm::TargetLoweringBase::setIntDivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 1060 of file TargetLowering.h.

1060 { IntDivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's required jmp_buf buffer alignment (in bytes); default is 0

Definition at line 1192 of file TargetLowering.h.

1192  {
1194  }
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotectedinherited

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1186 of file TargetLowering.h.

1186  {
1187  JumpBufSize = Size;
1188  }
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
void llvm::TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand sequence of operations into a separate sequences that increases the amount of flow control.

Definition at line 1053 of file TargetLowering.h.

1053  {
1054  JumpIsExpensive = isExpensive;
1055  }
void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inlineinherited

Set the CallingConv that should be used for the specified libcall.

Definition at line 1442 of file TargetLowering.h.

1442  {
1443  LibcallCallingConvs[Call] = CC;
1444  }
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char *  Name 
)
inlineinherited

Rename the default libcall routine name for the specified libcall.

Definition at line 1420 of file TargetLowering.h.

1420  {
1422  }
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

Definition at line 1110 of file TargetLowering.h.

1111  {
1113  "Table isn't big enough!");
1114  LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1115  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's minimum function alignment (in log2(bytes))

Definition at line 1197 of file TargetLowering.h.

1197  {
1199  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setMinimumJumpTableEntries ( int  Val)
inlineprotectedinherited

Indicate the number of blocks to generate jump tables rather than if sequence.

Definition at line 1006 of file TargetLowering.h.

1006  {
1008  }
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotectedinherited

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1216 of file TargetLowering.h.

1216  {
1218  }
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Definition at line 1102 of file TargetLowering.h.

1103  {
1104  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1105  OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1106  }
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
void llvm::TargetLoweringBase::setPow2DivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.

Definition at line 1069 of file TargetLowering.h.

1069 { Pow2DivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))

Definition at line 1204 of file TargetLowering.h.

1204  {
1206  }
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred loop alignment. Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes).

Definition at line 1211 of file TargetLowering.h.

1211  {
1213  }
unsigned PrefLoopAlignment
The preferred loop alignment.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotectedinherited

Specify the target scheduling preference.

Definition at line 983 of file TargetLowering.h.

983  {
984  SchedPreferenceInfo = Pref;
985  }
Sched::Preference SchedPreferenceInfo
void llvm::TargetLoweringBase::setSelectIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand operations into sequences that use the select operations if possible.

Definition at line 1030 of file TargetLowering.h.

1030  {
1031  SelectIsExpensive = isExpensive;
1032  }
void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 1012 of file TargetLowering.h.

1012  {
1014  }
unsigned StackPointerRegisterToSaveRestore
void llvm::TargetLoweringBase::setSupportJumpTables ( bool  Val)
inlineprotectedinherited

Indicate whether the target can generate code for jump tables.

Definition at line 1000 of file TargetLowering.h.

1000  {
1001  SupportJumpTables = Val;
1002  }
void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotectedinherited

Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Definition at line 1180 of file TargetLowering.h.

1180  {
1181  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1182  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1183  }
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

Definition at line 1119 of file TargetLowering.h.

1120  {
1121  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1122  "Table isn't big enough!");
1123  TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1124  }
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. Defaults to false.

Definition at line 995 of file TargetLowering.h.

995  {
996  UseUnderscoreLongJmp = Val;
997  }
void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. Defaults to false.

Definition at line 989 of file TargetLowering.h.

989  {
990  UseUnderscoreSetJmp = Val;
991  }
bool PPCTargetLowering::shouldConvertConstantLoadToIntImm ( const APInt Imm,
Type Ty 
) const
overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9171 of file PPCISelLowering.cpp.

9172  {
9173  assert(Ty->isIntegerTy());
9174 
9175  unsigned BitSize = Ty->getPrimitiveSizeInBits();
9176  if (BitSize == 0 || BitSize > 64)
9177  return false;
9178  return true;
9179 }
assert(Globals.size() > 1)
bool isIntegerTy() const
Definition: Type.h:193
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
virtual bool llvm::TargetLoweringBase::shouldExpandAtomicInIR ( Instruction Inst) const
inlinevirtualinherited

Return true if the given (atomic) instruction should be expanded by the IR-level AtomicExpandLoadLinked pass into a loop involving load-linked/store-conditional pairs. Atomic stores will be expanded in the same way as "atomic xchg" operations which ignore their output if needed.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 948 of file TargetLowering.h.

948  {
949  return false;
950  }
bool PPCTargetLowering::shouldExpandBuildVectorWithShuffles ( EVT  VT,
unsigned  DefinedValues 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 9256 of file PPCISelLowering.cpp.

9257  {
9258  if (VT == MVT::v2i64)
9259  return false;
9260 
9261  return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9262 }
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
virtual bool llvm::TargetLoweringBase::ShouldShrinkFPConstant ( EVT  ) const
inlinevirtualinherited

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented in llvm::X86TargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 726 of file TargetLowering.h.

726 { return true; }
bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt DemandedMask,
APInt KnownZero,
APInt KnownOne,
TargetLoweringOpt TLO,
unsigned  Depth = 0 
) const
inherited

Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 372 of file TargetLowering.cpp.

377  {
378  unsigned BitWidth = DemandedMask.getBitWidth();
379  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380  "Mask size mismatches value type size!");
381  APInt NewMask = DemandedMask;
382  SDLoc dl(Op);
383 
384  // Don't know anything.
385  KnownZero = KnownOne = APInt(BitWidth, 0);
386 
387  // Other users may use these bits.
388  if (!Op.getNode()->hasOneUse()) {
389  if (Depth != 0) {
390  // If not at the root, Just compute the KnownZero/KnownOne bits to
391  // simplify things downstream.
392  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
393  return false;
394  }
395  // If this is the root being simplified, allow it to have multiple uses,
396  // just set the NewMask to all bits.
397  NewMask = APInt::getAllOnesValue(BitWidth);
398  } else if (DemandedMask == 0) {
399  // Not demanding any bits from Op.
400  if (Op.getOpcode() != ISD::UNDEF)
401  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
402  return false;
403  } else if (Depth == 6) { // Limit search depth.
404  return false;
405  }
406 
407  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408  switch (Op.getOpcode()) {
409  case ISD::Constant:
410  // We know all of the bits for a constant!
411  KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412  KnownZero = ~KnownOne;
413  return false; // Don't fall through, will infinitely loop.
414  case ISD::AND:
415  // If the RHS is a constant, check to see if the LHS would be zero without
416  // using the bits from the RHS. Below, we use knowledge about the RHS to
417  // simplify the LHS, here we're using information from the LHS to simplify
418  // the RHS.
419  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420  APInt LHSZero, LHSOne;
421  // Do not increment Depth here; that can cause an infinite loop.
422  TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423  // If the LHS already has zeros where RHSC does, this and is dead.
424  if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425  return TLO.CombineTo(Op, Op.getOperand(0));
426  // If any of the set bits in the RHS are known zero on the LHS, shrink
427  // the constant.
428  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429  return true;
430  }
431 
432  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433  KnownOne, TLO, Depth+1))
434  return true;
435  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437  KnownZero2, KnownOne2, TLO, Depth+1))
438  return true;
439  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
440 
441  // If all of the demanded bits are known one on one side, return the other.
442  // These bits cannot contribute to the result of the 'and'.
443  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444  return TLO.CombineTo(Op, Op.getOperand(0));
445  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446  return TLO.CombineTo(Op, Op.getOperand(1));
447  // If all of the demanded bits in the inputs are known zeros, return zero.
448  if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450  // If the RHS is a constant, see if we can simplify it.
451  if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
452  return true;
453  // If the operation can be done in a smaller type, do so.
454  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
455  return true;
456 
457  // Output known-1 bits are only known if set in both the LHS & RHS.
458  KnownOne &= KnownOne2;
459  // Output known-0 are known to be clear if zero in either the LHS | RHS.
460  KnownZero |= KnownZero2;
461  break;
462  case ISD::OR:
463  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464  KnownOne, TLO, Depth+1))
465  return true;
466  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468  KnownZero2, KnownOne2, TLO, Depth+1))
469  return true;
470  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
471 
472  // If all of the demanded bits are known zero on one side, return the other.
473  // These bits cannot contribute to the result of the 'or'.
474  if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475  return TLO.CombineTo(Op, Op.getOperand(0));
476  if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477  return TLO.CombineTo(Op, Op.getOperand(1));
478  // If all of the potentially set bits on one side are known to be set on
479  // the other side, just use the 'other' side.
480  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481  return TLO.CombineTo(Op, Op.getOperand(0));
482  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483  return TLO.CombineTo(Op, Op.getOperand(1));
484  // If the RHS is a constant, see if we can simplify it.
485  if (TLO.ShrinkDemandedConstant(Op, NewMask))
486  return true;
487  // If the operation can be done in a smaller type, do so.
488  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
489  return true;
490 
491  // Output known-0 bits are only known if clear in both the LHS & RHS.
492  KnownZero &= KnownZero2;
493  // Output known-1 are known to be set if set in either the LHS | RHS.
494  KnownOne |= KnownOne2;
495  break;
496  case ISD::XOR:
497  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498  KnownOne, TLO, Depth+1))
499  return true;
500  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502  KnownOne2, TLO, Depth+1))
503  return true;
504  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
505 
506  // If all of the demanded bits are known zero on one side, return the other.
507  // These bits cannot contribute to the result of the 'xor'.
508  if ((KnownZero & NewMask) == NewMask)
509  return TLO.CombineTo(Op, Op.getOperand(0));
510  if ((KnownZero2 & NewMask) == NewMask)
511  return TLO.CombineTo(Op, Op.getOperand(1));
512  // If the operation can be done in a smaller type, do so.
513  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
514  return true;
515 
516  // If all of the unknown bits are known to be zero on one side or the other
517  // (but not both) turn this into an *inclusive* or.
518  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519  if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521  Op.getOperand(0),
522  Op.getOperand(1)));
523 
524  // Output known-0 bits are known if clear or set in both the LHS & RHS.
525  KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526  // Output known-1 are known to be set if set in only one of the LHS, RHS.
527  KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
528 
529  // If all of the demanded bits on one side are known, and all of the set
530  // bits on that side are also known to be set on the other side, turn this
531  // into an AND, as we know the bits will be cleared.
532  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533  // NB: it is okay if more bits are known than are requested
534  if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535  if (KnownOne == KnownOne2) { // set bits are the same on both sides
536  EVT VT = Op.getValueType();
537  SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539  Op.getOperand(0), ANDC));
540  }
541  }
542 
543  // If the RHS is a constant, see if we can simplify it.
544  // for XOR, we prefer to force bits to 1 if they will make a -1.
545  // if we can't force bits, try to shrink constant
546  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547  APInt Expanded = C->getAPIntValue() | (~NewMask);
548  // if we can expand it to have all bits set, do it
549  if (Expanded.isAllOnesValue()) {
550  if (Expanded != C->getAPIntValue()) {
551  EVT VT = Op.getValueType();
552  SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553  TLO.DAG.getConstant(Expanded, VT));
554  return TLO.CombineTo(Op, New);
555  }
556  // if it already has all the bits set, nothing to change
557  // but don't shrink either!
558  } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
559  return true;
560  }
561  }
562 
563  KnownZero = KnownZeroOut;
564  KnownOne = KnownOneOut;
565  break;
566  case ISD::SELECT:
567  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568  KnownOne, TLO, Depth+1))
569  return true;
570  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571  KnownOne2, TLO, Depth+1))
572  return true;
573  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
575 
576  // If the operands are constants, see if we can simplify them.
577  if (TLO.ShrinkDemandedConstant(Op, NewMask))
578  return true;
579 
580  // Only known if known in both the LHS and RHS.
581  KnownOne &= KnownOne2;
582  KnownZero &= KnownZero2;
583  break;
584  case ISD::SELECT_CC:
585  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586  KnownOne, TLO, Depth+1))
587  return true;
588  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589  KnownOne2, TLO, Depth+1))
590  return true;
591  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
593 
594  // If the operands are constants, see if we can simplify them.
595  if (TLO.ShrinkDemandedConstant(Op, NewMask))
596  return true;
597 
598  // Only known if known in both the LHS and RHS.
599  KnownOne &= KnownOne2;
600  KnownZero &= KnownZero2;
601  break;
602  case ISD::SHL:
603  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604  unsigned ShAmt = SA->getZExtValue();
605  SDValue InOp = Op.getOperand(0);
606 
607  // If the shift count is an invalid immediate, don't do anything.
608  if (ShAmt >= BitWidth)
609  break;
610 
611  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612  // single shift. We can do this if the bottom bits (which are shifted
613  // out) are never demanded.
614  if (InOp.getOpcode() == ISD::SRL &&
615  isa<ConstantSDNode>(InOp.getOperand(1))) {
616  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618  unsigned Opc = ISD::SHL;
619  int Diff = ShAmt-C1;
620  if (Diff < 0) {
621  Diff = -Diff;
622  Opc = ISD::SRL;
623  }
624 
625  SDValue NewSA =
626  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627  EVT VT = Op.getValueType();
628  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629  InOp.getOperand(0), NewSA));
630  }
631  }
632 
633  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634  KnownZero, KnownOne, TLO, Depth+1))
635  return true;
636 
637  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638  // are not demanded. This will likely allow the anyext to be folded away.
639  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640  SDValue InnerOp = InOp.getNode()->getOperand(0);
641  EVT InnerVT = InnerOp.getValueType();
642  unsigned InnerBits = InnerVT.getSizeInBits();
643  if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645  EVT ShTy = getShiftAmountTy(InnerVT);
646  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
647  ShTy = InnerVT;
648  SDValue NarrowShl =
649  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650  TLO.DAG.getConstant(ShAmt, ShTy));
651  return
652  TLO.CombineTo(Op,
653  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
654  NarrowShl));
655  }
656  // Repeat the SHL optimization above in cases where an extension
657  // intervenes: (shl (anyext (shr x, c1)), c2) to
658  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659  // aren't demanded (as above) and that the shifted upper c1 bits of
660  // x aren't demanded.
661  if (InOp.hasOneUse() &&
662  InnerOp.getOpcode() == ISD::SRL &&
663  InnerOp.hasOneUse() &&
664  isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665  uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
666  ->getZExtValue();
667  if (InnerShAmt < ShAmt &&
668  InnerShAmt < InnerBits &&
669  NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670  NewMask.trunc(ShAmt) == 0) {
671  SDValue NewSA =
672  TLO.DAG.getConstant(ShAmt - InnerShAmt,
673  Op.getOperand(1).getValueType());
674  EVT VT = Op.getValueType();
675  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676  InnerOp.getOperand(0));
677  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
678  NewExt, NewSA));
679  }
680  }
681  }
682 
683  KnownZero <<= SA->getZExtValue();
684  KnownOne <<= SA->getZExtValue();
685  // low bits known zero.
686  KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687  }
688  break;
689  case ISD::SRL:
690  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691  EVT VT = Op.getValueType();
692  unsigned ShAmt = SA->getZExtValue();
693  unsigned VTSize = VT.getSizeInBits();
694  SDValue InOp = Op.getOperand(0);
695 
696  // If the shift count is an invalid immediate, don't do anything.
697  if (ShAmt >= BitWidth)
698  break;
699 
700  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701  // single shift. We can do this if the top bits (which are shifted out)
702  // are never demanded.
703  if (InOp.getOpcode() == ISD::SHL &&
704  isa<ConstantSDNode>(InOp.getOperand(1))) {
705  if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707  unsigned Opc = ISD::SRL;
708  int Diff = ShAmt-C1;
709  if (Diff < 0) {
710  Diff = -Diff;
711  Opc = ISD::SHL;
712  }
713 
714  SDValue NewSA =
715  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717  InOp.getOperand(0), NewSA));
718  }
719  }
720 
721  // Compute the new bits that are at the top now.
722  if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723  KnownZero, KnownOne, TLO, Depth+1))
724  return true;
725  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726  KnownZero = KnownZero.lshr(ShAmt);
727  KnownOne = KnownOne.lshr(ShAmt);
728 
729  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730  KnownZero |= HighBits; // High bits known zero.
731  }
732  break;
733  case ISD::SRA:
734  // If this is an arithmetic shift right and only the low-bit is set, we can
735  // always convert this into a logical shr, even if the shift amount is
736  // variable. The low bit of the shift cannot be an input sign bit unless
737  // the shift amount is >= the size of the datatype, which is undefined.
738  if (NewMask == 1)
739  return TLO.CombineTo(Op,
740  TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741  Op.getOperand(0), Op.getOperand(1)));
742 
743  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744  EVT VT = Op.getValueType();
745  unsigned ShAmt = SA->getZExtValue();
746 
747  // If the shift count is an invalid immediate, don't do anything.
748  if (ShAmt >= BitWidth)
749  break;
750 
751  APInt InDemandedMask = (NewMask << ShAmt);
752 
753  // If any of the demanded bits are produced by the sign extension, we also
754  // demand the input sign bit.
755  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756  if (HighBits.intersects(NewMask))
757  InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
758 
759  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760  KnownZero, KnownOne, TLO, Depth+1))
761  return true;
762  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763  KnownZero = KnownZero.lshr(ShAmt);
764  KnownOne = KnownOne.lshr(ShAmt);
765 
766  // Handle the sign bit, adjusted to where it is now in the mask.
767  APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
768 
769  // If the input sign bit is known to be zero, or if none of the top bits
770  // are demanded, turn this into an unsigned shift right.
771  if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773  Op.getOperand(0),
774  Op.getOperand(1)));
775 
776  int Log2 = NewMask.exactLogBase2();
777  if (Log2 >= 0) {
778  // The bit must come from the sign.
779  SDValue NewSA =
780  TLO.DAG.getConstant(BitWidth - 1 - Log2,
781  Op.getOperand(1).getValueType());
782  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783  Op.getOperand(0), NewSA));
784  }
785 
786  if (KnownOne.intersects(SignBit))
787  // New bits are known one.
788  KnownOne |= HighBits;
789  }
790  break;
791  case ISD::SIGN_EXTEND_INREG: {
792  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
793 
794  APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795  // If we only care about the highest bit, don't bother shifting right.
796  if (MsbMask == DemandedMask) {
797  unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798  SDValue InOp = Op.getOperand(0);
799 
800  // Compute the correct shift amount type, which must be getShiftAmountTy
801  // for scalar types after legalization.
802  EVT ShiftAmtTy = Op.getValueType();
803  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
804  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
805 
806  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
807  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
808  Op.getValueType(), InOp, ShiftAmt));
809  }
810 
811  // Sign extension. Compute the demanded bits in the result that are not
812  // present in the input.
813  APInt NewBits =
814  APInt::getHighBitsSet(BitWidth,
815  BitWidth - ExVT.getScalarType().getSizeInBits());
816 
817  // If none of the extended bits are demanded, eliminate the sextinreg.
818  if ((NewBits & NewMask) == 0)
819  return TLO.CombineTo(Op, Op.getOperand(0));
820 
821  APInt InSignBit =
822  APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
823  APInt InputDemandedBits =
824  APInt::getLowBitsSet(BitWidth,
825  ExVT.getScalarType().getSizeInBits()) &
826  NewMask;
827 
828  // Since the sign extended bits are demanded, we know that the sign
829  // bit is demanded.
830  InputDemandedBits |= InSignBit;
831 
832  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
833  KnownZero, KnownOne, TLO, Depth+1))
834  return true;
835  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
836 
837  // If the sign bit of the input is known set or clear, then we know the
838  // top bits of the result.
839 
840  // If the input sign bit is known zero, convert this into a zero extension.
841  if (KnownZero.intersects(InSignBit))
842  return TLO.CombineTo(Op,
843  TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
844 
845  if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
846  KnownOne |= NewBits;
847  KnownZero &= ~NewBits;
848  } else { // Input sign bit unknown
849  KnownZero &= ~NewBits;
850  KnownOne &= ~NewBits;
851  }
852  break;
853  }
854  case ISD::BUILD_PAIR: {
855  EVT HalfVT = Op.getOperand(0).getValueType();
856  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
857 
858  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
859  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
860 
861  APInt KnownZeroLo, KnownOneLo;
862  APInt KnownZeroHi, KnownOneHi;
863 
864  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
865  KnownOneLo, TLO, Depth + 1))
866  return true;
867 
868  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
869  KnownOneHi, TLO, Depth + 1))
870  return true;
871 
872  KnownZero = KnownZeroLo.zext(BitWidth) |
873  KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
874 
875  KnownOne = KnownOneLo.zext(BitWidth) |
876  KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
877  break;
878  }
879  case ISD::ZERO_EXTEND: {
880  unsigned OperandBitWidth =
882  APInt InMask = NewMask.trunc(OperandBitWidth);
883 
884  // If none of the top bits are demanded, convert this into an any_extend.
885  APInt NewBits =
886  APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
887  if (!NewBits.intersects(NewMask))
888  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
889  Op.getValueType(),
890  Op.getOperand(0)));
891 
892  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
893  KnownZero, KnownOne, TLO, Depth+1))
894  return true;
895  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896  KnownZero = KnownZero.zext(BitWidth);
897  KnownOne = KnownOne.zext(BitWidth);
898  KnownZero |= NewBits;
899  break;
900  }
901  case ISD::SIGN_EXTEND: {
902  EVT InVT = Op.getOperand(0).getValueType();
903  unsigned InBits = InVT.getScalarType().getSizeInBits();
904  APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
905  APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
906  APInt NewBits = ~InMask & NewMask;
907 
908  // If none of the top bits are demanded, convert this into an any_extend.
909  if (NewBits == 0)
910  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
911  Op.getValueType(),
912  Op.getOperand(0)));
913 
914  // Since some of the sign extended bits are demanded, we know that the sign
915  // bit is demanded.
916  APInt InDemandedBits = InMask & NewMask;
917  InDemandedBits |= InSignBit;
918  InDemandedBits = InDemandedBits.trunc(InBits);
919 
920  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
921  KnownOne, TLO, Depth+1))
922  return true;
923  KnownZero = KnownZero.zext(BitWidth);
924  KnownOne = KnownOne.zext(BitWidth);
925 
926  // If the sign bit is known zero, convert this to a zero extend.
927  if (KnownZero.intersects(InSignBit))
928  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
929  Op.getValueType(),
930  Op.getOperand(0)));
931 
932  // If the sign bit is known one, the top bits match.
933  if (KnownOne.intersects(InSignBit)) {
934  KnownOne |= NewBits;
935  assert((KnownZero & NewBits) == 0);
936  } else { // Otherwise, top bits aren't known.
937  assert((KnownOne & NewBits) == 0);
938  assert((KnownZero & NewBits) == 0);
939  }
940  break;
941  }
942  case ISD::ANY_EXTEND: {
943  unsigned OperandBitWidth =
945  APInt InMask = NewMask.trunc(OperandBitWidth);
946  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
947  KnownZero, KnownOne, TLO, Depth+1))
948  return true;
949  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
950  KnownZero = KnownZero.zext(BitWidth);
951  KnownOne = KnownOne.zext(BitWidth);
952  break;
953  }
954  case ISD::TRUNCATE: {
955  // Simplify the input, using demanded bit information, and compute the known
956  // zero/one bits live out.
957  unsigned OperandBitWidth =
959  APInt TruncMask = NewMask.zext(OperandBitWidth);
960  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
961  KnownZero, KnownOne, TLO, Depth+1))
962  return true;
963  KnownZero = KnownZero.trunc(BitWidth);
964  KnownOne = KnownOne.trunc(BitWidth);
965 
966  // If the input is only used by this truncate, see if we can shrink it based
967  // on the known demanded bits.
968  if (Op.getOperand(0).getNode()->hasOneUse()) {
969  SDValue In = Op.getOperand(0);
970  switch (In.getOpcode()) {
971  default: break;
972  case ISD::SRL:
973  // Shrink SRL by a constant if none of the high bits shifted in are
974  // demanded.
975  if (TLO.LegalTypes() &&
977  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
978  // undesirable.
979  break;
981  if (!ShAmt)
982  break;
983  SDValue Shift = In.getOperand(1);
984  if (TLO.LegalTypes()) {
985  uint64_t ShVal = ShAmt->getZExtValue();
986  Shift =
987  TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
988  }
989 
990  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
991  OperandBitWidth - BitWidth);
992  HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
993 
994  if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
995  // None of the shifted in bits are needed. Add a truncate of the
996  // shift input, then shift it.
997  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
998  Op.getValueType(),
999  In.getOperand(0));
1000  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1001  Op.getValueType(),
1002  NewTrunc,
1003  Shift));
1004  }
1005  break;
1006  }
1007  }
1008 
1009  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1010  break;
1011  }
1012  case ISD::AssertZext: {
1013  // AssertZext demands all of the high bits, plus any of the low bits
1014  // demanded by its users.
1015  EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1016  APInt InMask = APInt::getLowBitsSet(BitWidth,
1017  VT.getSizeInBits());
1018  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1019  KnownZero, KnownOne, TLO, Depth+1))
1020  return true;
1021  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1022 
1023  KnownZero |= ~InMask & NewMask;
1024  break;
1025  }
1026  case ISD::BITCAST:
1027  // If this is an FP->Int bitcast and if the sign bit is the only
1028  // thing demanded, turn this into a FGETSIGN.
1029  if (!TLO.LegalOperations() &&
1030  !Op.getValueType().isVector() &&
1031  !Op.getOperand(0).getValueType().isVector() &&
1032  NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1034  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1036  if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1037  EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1038  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1039  // place. We expect the SHL to be eliminated by other optimizations.
1040  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1041  unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1042  if (!OpVTLegal && OpVTSizeInBits > 32)
1043  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1044  unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1045  SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1046  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1047  Op.getValueType(),
1048  Sign, ShAmt));
1049  }
1050  }
1051  break;
1052  case ISD::ADD:
1053  case ISD::MUL:
1054  case ISD::SUB: {
1055  // Add, Sub, and Mul don't demand any bits in positions beyond that
1056  // of the highest bit demanded of them.
1057  APInt LoMask = APInt::getLowBitsSet(BitWidth,
1058  BitWidth - NewMask.countLeadingZeros());
1059  if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1060  KnownOne2, TLO, Depth+1))
1061  return true;
1062  if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1063  KnownOne2, TLO, Depth+1))
1064  return true;
1065  // See if the operation should be performed at a smaller bit width.
1066  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1067  return true;
1068  }
1069  // FALL THROUGH
1070  default:
1071  // Just use computeKnownBits to compute output bits.
1072  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1073  break;
1074  }
1075 
1076  // If we know the value of all of the demanded bits, return this as a
1077  // constant.
1078  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1079  return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1080 
1081  return false;
1082 }
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
unsigned getOpcode() const
const SDValue & getOperand(unsigned Num) const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
double trunc(double x);
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
EVT getShiftAmountTy(EVT LHSTy) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
EVT getScalarType() const
Definition: ValueTypes.h:211
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:852
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
assert(Globals.size() > 1)
bool intersects(const APInt &RHS) const
Definition: APInt.h:1140
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:920
const SDValue & getOperand(unsigned i) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:677
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
bool isIntN(unsigned N, int64_t x)
Definition: MathExtras.h:330
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:672
int32_t exactLogBase2() const
Definition: APInt.h:1534
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:493
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:338
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
EVT getValueType() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
bool isSimple() const
Definition: ValueTypes.h:95
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:984
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
uint64_t getZExtValue() const
SDValue TargetLowering::SimplifySetCC ( EVT  VT,
SDValue  N0,
SDValue  N1,
ISD::CondCode  Cond,
bool  foldBooleans,
DAGCombinerInfo DCI,
SDLoc  dl 
) const
inherited

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Definition at line 1206 of file TargetLowering.cpp.

1208  {
1209  SelectionDAG &DAG = DCI.DAG;
1210 
1211  // These setcc operations always fold.
1212  switch (Cond) {
1213  default: break;
1214  case ISD::SETFALSE:
1215  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1216  case ISD::SETTRUE:
1217  case ISD::SETTRUE2: {
1220  return DAG.getConstant(
1221  Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1222  }
1223  }
1224 
1225  // Ensure that the constant occurs on the RHS, and fold constant
1226  // comparisons.
1227  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1228  if (isa<ConstantSDNode>(N0.getNode()) &&
1229  (DCI.isBeforeLegalizeOps() ||
1230  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1231  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1232 
1233  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1234  const APInt &C1 = N1C->getAPIntValue();
1235 
1236  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1237  // equality comparison, then we're just comparing whether X itself is
1238  // zero.
1239  if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241  N0.getOperand(1).getOpcode() == ISD::Constant) {
1242  const APInt &ShAmt
1243  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1244  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1245  ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1246  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1247  // (srl (ctlz x), 5) == 0 -> X != 0
1248  // (srl (ctlz x), 5) != 1 -> X != 0
1249  Cond = ISD::SETNE;
1250  } else {
1251  // (srl (ctlz x), 5) != 0 -> X == 0
1252  // (srl (ctlz x), 5) == 1 -> X == 0
1253  Cond = ISD::SETEQ;
1254  }
1255  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1256  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1257  Zero, Cond);
1258  }
1259  }
1260 
1261  SDValue CTPOP = N0;
1262  // Look through truncs that don't change the value of a ctpop.
1263  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1264  CTPOP = N0.getOperand(0);
1265 
1266  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1267  (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1268  Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1269  EVT CTVT = CTPOP.getValueType();
1270  SDValue CTOp = CTPOP.getOperand(0);
1271 
1272  // (ctpop x) u< 2 -> (x & x-1) == 0
1273  // (ctpop x) u> 1 -> (x & x-1) != 0
1274  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1275  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1276  DAG.getConstant(1, CTVT));
1277  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1279  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1280  }
1281 
1282  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1283  }
1284 
1285  // (zext x) == C --> x == (trunc C)
1286  if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1287  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1288  unsigned MinBits = N0.getValueSizeInBits();
1289  SDValue PreZExt;
1290  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1291  // ZExt
1292  MinBits = N0->getOperand(0).getValueSizeInBits();
1293  PreZExt = N0->getOperand(0);
1294  } else if (N0->getOpcode() == ISD::AND) {
1295  // DAGCombine turns costly ZExts into ANDs
1296  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1297  if ((C->getAPIntValue()+1).isPowerOf2()) {
1298  MinBits = C->getAPIntValue().countTrailingOnes();
1299  PreZExt = N0->getOperand(0);
1300  }
1301  } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1302  // ZEXTLOAD
1303  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1304  MinBits = LN0->getMemoryVT().getSizeInBits();
1305  PreZExt = N0;
1306  }
1307  }
1308 
1309  // Make sure we're not losing bits from the constant.
1310  if (MinBits > 0 &&
1311  MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1312  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1313  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1314  // Will get folded away.
1315  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1316  SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1317  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1318  }
1319  }
1320  }
1321 
1322  // If the LHS is '(and load, const)', the RHS is 0,
1323  // the test is for equality or unsigned, and all 1 bits of the const are
1324  // in the same partial word, see if we can shorten the load.
1325  if (DCI.isBeforeLegalize() &&
1326  !ISD::isSignedIntSetCC(Cond) &&
1327  N0.getOpcode() == ISD::AND && C1 == 0 &&
1328  N0.getNode()->hasOneUse() &&
1329  isa<LoadSDNode>(N0.getOperand(0)) &&
1330  N0.getOperand(0).getNode()->hasOneUse() &&
1331  isa<ConstantSDNode>(N0.getOperand(1))) {
1332  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1333  APInt bestMask;
1334  unsigned bestWidth = 0, bestOffset = 0;
1335  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1336  unsigned origWidth = N0.getValueType().getSizeInBits();
1337  unsigned maskWidth = origWidth;
1338  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1339  // 8 bits, but have to be careful...
1340  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1341  origWidth = Lod->getMemoryVT().getSizeInBits();
1342  const APInt &Mask =
1343  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1344  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1345  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1346  for (unsigned offset=0; offset<origWidth/width; offset++) {
1347  if ((newMask & Mask) == Mask) {
1348  if (!getDataLayout()->isLittleEndian())
1349  bestOffset = (origWidth/width - offset - 1) * (width/8);
1350  else
1351  bestOffset = (uint64_t)offset * (width/8);
1352  bestMask = Mask.lshr(offset * (width/8) * 8);
1353  bestWidth = width;
1354  break;
1355  }
1356  newMask = newMask << width;
1357  }
1358  }
1359  }
1360  if (bestWidth) {
1361  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1362  if (newVT.isRound()) {
1363  EVT PtrType = Lod->getOperand(1).getValueType();
1364  SDValue Ptr = Lod->getBasePtr();
1365  if (bestOffset != 0)
1366  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1367  DAG.getConstant(bestOffset, PtrType));
1368  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1369  SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1370  Lod->getPointerInfo().getWithOffset(bestOffset),
1371  false, false, false, NewAlign);
1372  return DAG.getSetCC(dl, VT,
1373  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1374  DAG.getConstant(bestMask.trunc(bestWidth),
1375  newVT)),
1376  DAG.getConstant(0LL, newVT), Cond);
1377  }
1378  }
1379  }
1380 
1381  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1382  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1383  unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1384 
1385  // If the comparison constant has bits in the upper part, the
1386  // zero-extended value could never match.
1387  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1388  C1.getBitWidth() - InSize))) {
1389  switch (Cond) {
1390  case ISD::SETUGT:
1391  case ISD::SETUGE:
1392  case ISD::SETEQ: return DAG.getConstant(0, VT);
1393  case ISD::SETULT:
1394  case ISD::SETULE:
1395  case ISD::SETNE: return DAG.getConstant(1, VT);
1396  case ISD::SETGT:
1397  case ISD::SETGE:
1398  // True if the sign bit of C1 is set.
1399  return DAG.getConstant(C1.isNegative(), VT);
1400  case ISD::SETLT:
1401  case ISD::SETLE:
1402  // True if the sign bit of C1 isn't set.
1403  return DAG.getConstant(C1.isNonNegative(), VT);
1404  default:
1405  break;
1406  }
1407  }
1408 
1409  // Otherwise, we can perform the comparison with the low bits.
1410  switch (Cond) {
1411  case ISD::SETEQ:
1412  case ISD::SETNE:
1413  case ISD::SETUGT:
1414  case ISD::SETUGE:
1415  case ISD::SETULT:
1416  case ISD::SETULE: {
1417  EVT newVT = N0.getOperand(0).getValueType();
1418  if (DCI.isBeforeLegalizeOps() ||
1419  (isOperationLegal(ISD::SETCC, newVT) &&
1420  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1421  EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1422  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1423 
1424  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1425  NewConst, Cond);
1426  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1427  }
1428  break;
1429  }
1430  default:
1431  break; // todo, be more careful with signed comparisons
1432  }
1433  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1434  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1435  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1436  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1437  EVT ExtDstTy = N0.getValueType();
1438  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1439 
1440  // If the constant doesn't fit into the number of bits for the source of
1441  // the sign extension, it is impossible for both sides to be equal.
1442  if (C1.getMinSignedBits() > ExtSrcTyBits)
1443  return DAG.getConstant(Cond == ISD::SETNE, VT);
1444 
1445  SDValue ZextOp;
1446  EVT Op0Ty = N0.getOperand(0).getValueType();
1447  if (Op0Ty == ExtSrcTy) {
1448  ZextOp = N0.getOperand(0);
1449  } else {
1450  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1451  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1452  DAG.getConstant(Imm, Op0Ty));
1453  }
1454  if (!DCI.isCalledByLegalizer())
1455  DCI.AddToWorklist(ZextOp.getNode());
1456  // Otherwise, make this a use of a zext.
1457  return DAG.getSetCC(dl, VT, ZextOp,
1459  ExtDstTyBits,
1460  ExtSrcTyBits),
1461  ExtDstTy),
1462  Cond);
1463  } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1464  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1465  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1466  if (N0.getOpcode() == ISD::SETCC &&
1467  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1468  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1469  if (TrueWhenTrue)
1470  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1471  // Invert the condition.
1472  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1473  CC = ISD::getSetCCInverse(CC,
1474  N0.getOperand(0).getValueType().isInteger());
1475  if (DCI.isBeforeLegalizeOps() ||
1476  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1477  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1478  }
1479 
1480  if ((N0.getOpcode() == ISD::XOR ||
1481  (N0.getOpcode() == ISD::AND &&
1482  N0.getOperand(0).getOpcode() == ISD::XOR &&
1483  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1484  isa<ConstantSDNode>(N0.getOperand(1)) &&
1485  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1486  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1487  // can only do this if the top bits are known zero.
1488  unsigned BitWidth = N0.getValueSizeInBits();
1489  if (DAG.MaskedValueIsZero(N0,
1490  APInt::getHighBitsSet(BitWidth,
1491  BitWidth-1))) {
1492  // Okay, get the un-inverted input value.
1493  SDValue Val;
1494  if (N0.getOpcode() == ISD::XOR)
1495  Val = N0.getOperand(0);
1496  else {
1497  assert(N0.getOpcode() == ISD::AND &&
1498  N0.getOperand(0).getOpcode() == ISD::XOR);
1499  // ((X^1)&1)^1 -> X & 1
1500  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1501  N0.getOperand(0).getOperand(0),
1502  N0.getOperand(1));
1503  }
1504 
1505  return DAG.getSetCC(dl, VT, Val, N1,
1506  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1507  }
1508  } else if (N1C->getAPIntValue() == 1 &&
1509  (VT == MVT::i1 ||
1510  getBooleanContents(N0->getValueType(0)) ==
1512  SDValue Op0 = N0;
1513  if (Op0.getOpcode() == ISD::TRUNCATE)
1514  Op0 = Op0.getOperand(0);
1515 
1516  if ((Op0.getOpcode() == ISD::XOR) &&
1517  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1518  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1519  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1520  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1521  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1522  Cond);
1523  }
1524  if (Op0.getOpcode() == ISD::AND &&
1525  isa<ConstantSDNode>(Op0.getOperand(1)) &&
1526  cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1527  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1528  if (Op0.getValueType().bitsGT(VT))
1529  Op0 = DAG.getNode(ISD::AND, dl, VT,
1530  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1531  DAG.getConstant(1, VT));
1532  else if (Op0.getValueType().bitsLT(VT))
1533  Op0 = DAG.getNode(ISD::AND, dl, VT,
1534  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1535  DAG.getConstant(1, VT));
1536 
1537  return DAG.getSetCC(dl, VT, Op0,
1538  DAG.getConstant(0, Op0.getValueType()),
1539  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1540  }
1541  if (Op0.getOpcode() == ISD::AssertZext &&
1542  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1543  return DAG.getSetCC(dl, VT, Op0,
1544  DAG.getConstant(0, Op0.getValueType()),
1545  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1546  }
1547  }
1548 
1549  APInt MinVal, MaxVal;
1550  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1551  if (ISD::isSignedIntSetCC(Cond)) {
1552  MinVal = APInt::getSignedMinValue(OperandBitSize);
1553  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1554  } else {
1555  MinVal = APInt::getMinValue(OperandBitSize);
1556  MaxVal = APInt::getMaxValue(OperandBitSize);
1557  }
1558 
1559  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1560  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1561  if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1562  // X >= C0 --> X > (C0 - 1)
1563  APInt C = C1 - 1;
1564  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1565  if ((DCI.isBeforeLegalizeOps() ||
1566  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1567  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1569  return DAG.getSetCC(dl, VT, N0,
1570  DAG.getConstant(C, N1.getValueType()),
1571  NewCC);
1572  }
1573  }
1574 
1575  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1576  if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1577  // X <= C0 --> X < (C0 + 1)
1578  APInt C = C1 + 1;
1579  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1580  if ((DCI.isBeforeLegalizeOps() ||
1581  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1582  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1584  return DAG.getSetCC(dl, VT, N0,
1585  DAG.getConstant(C, N1.getValueType()),
1586  NewCC);
1587  }
1588  }
1589 
1590  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1591  return DAG.getConstant(0, VT); // X < MIN --> false
1592  if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1593  return DAG.getConstant(1, VT); // X >= MIN --> true
1594  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1595  return DAG.getConstant(0, VT); // X > MAX --> false
1596  if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1597  return DAG.getConstant(1, VT); // X <= MAX --> true
1598 
1599  // Canonicalize setgt X, Min --> setne X, Min
1600  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1601  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1602  // Canonicalize setlt X, Max --> setne X, Max
1603  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1604  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1605 
1606  // If we have setult X, 1, turn it into seteq X, 0
1607  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1608  return DAG.getSetCC(dl, VT, N0,
1609  DAG.getConstant(MinVal, N0.getValueType()),
1610  ISD::SETEQ);
1611  // If we have setugt X, Max-1, turn it into seteq X, Max
1612  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1613  return DAG.getSetCC(dl, VT, N0,
1614  DAG.getConstant(MaxVal, N0.getValueType()),
1615  ISD::SETEQ);
1616 
1617  // If we have "setcc X, C0", check to see if we can shrink the immediate
1618  // by changing cc.
1619 
1620  // SETUGT X, SINTMAX -> SETLT X, 0
1621  if (Cond == ISD::SETUGT &&
1622  C1 == APInt::getSignedMaxValue(OperandBitSize))
1623  return DAG.getSetCC(dl, VT, N0,
1624  DAG.getConstant(0, N1.getValueType()),
1625  ISD::SETLT);
1626 
1627  // SETULT X, SINTMIN -> SETGT X, -1
1628  if (Cond == ISD::SETULT &&
1629  C1 == APInt::getSignedMinValue(OperandBitSize)) {
1630  SDValue ConstMinusOne =
1631  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1632  N1.getValueType());
1633  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1634  }
1635 
1636  // Fold bit comparisons when we can.
1637  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1638  (VT == N0.getValueType() ||
1639  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1640  N0.getOpcode() == ISD::AND)
1641  if (ConstantSDNode *AndRHS =
1642  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1643  EVT ShiftTy = DCI.isBeforeLegalize() ?
1645  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1646  // Perform the xform if the AND RHS is a single bit.
1647  if (AndRHS->getAPIntValue().isPowerOf2()) {
1648  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1650  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1651  }
1652  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1653  // (X & 8) == 8 --> (X & 8) >> 3
1654  // Perform the xform if C1 is a single bit.
1655  if (C1.isPowerOf2()) {
1656  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1657  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1658  DAG.getConstant(C1.logBase2(), ShiftTy)));
1659  }
1660  }
1661  }
1662 
1663  if (C1.getMinSignedBits() <= 64 &&
1664  !isLegalICmpImmediate(C1.getSExtValue())) {
1665  // (X & -256) == 256 -> (X >> 8) == 1
1666  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1667  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1668  if (ConstantSDNode *AndRHS =
1669  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1670  const APInt &AndRHSC = AndRHS->getAPIntValue();
1671  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1672  unsigned ShiftBits = AndRHSC.countTrailingZeros();
1673  EVT ShiftTy = DCI.isBeforeLegalize() ?
1675  EVT CmpTy = N0.getValueType();
1676  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1677  DAG.getConstant(ShiftBits, ShiftTy));
1678  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1679  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1680  }
1681  }
1682  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1683  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1684  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1685  // X < 0x100000000 -> (X >> 32) < 1
1686  // X >= 0x100000000 -> (X >> 32) >= 1
1687  // X <= 0x0ffffffff -> (X >> 32) < 1
1688  // X > 0x0ffffffff -> (X >> 32) >= 1
1689  unsigned ShiftBits;
1690  APInt NewC = C1;
1691  ISD::CondCode NewCond = Cond;
1692  if (AdjOne) {
1693  ShiftBits = C1.countTrailingOnes();
1694  NewC = NewC + 1;
1695  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1696  } else {
1697  ShiftBits = C1.countTrailingZeros();
1698  }
1699  NewC = NewC.lshr(ShiftBits);
1700  if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1701  EVT ShiftTy = DCI.isBeforeLegalize() ?
1703  EVT CmpTy = N0.getValueType();
1704  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1705  DAG.getConstant(ShiftBits, ShiftTy));
1706  SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1707  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1708  }
1709  }
1710  }
1711  }
1712 
1713  if (isa<ConstantFPSDNode>(N0.getNode())) {
1714  // Constant fold or commute setcc.
1715  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1716  if (O.getNode()) return O;
1717  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1718  // If the RHS of an FP comparison is a constant, simplify it away in
1719  // some cases.
1720  if (CFP->getValueAPF().isNaN()) {
1721  // If an operand is known to be a nan, we can fold it.
1722  switch (ISD::getUnorderedFlavor(Cond)) {
1723  default: llvm_unreachable("Unknown flavor!");
1724  case 0: // Known false.
1725  return DAG.getConstant(0, VT);
1726  case 1: // Known true.
1727  return DAG.getConstant(1, VT);
1728  case 2: // Undefined.
1729  return DAG.getUNDEF(VT);
1730  }
1731  }
1732 
1733  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1734  // constant if knowing that the operand is non-nan is enough. We prefer to
1735  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1736  // materialize 0.0.
1737  if (Cond == ISD::SETO || Cond == ISD::SETUO)
1738  return DAG.getSetCC(dl, VT, N0, N0, Cond);
1739 
1740  // If the condition is not legal, see if we can find an equivalent one
1741  // which is legal.
1742  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1743  // If the comparison was an awkward floating-point == or != and one of
1744  // the comparison operands is infinity or negative infinity, convert the
1745  // condition to a less-awkward <= or >=.
1746  if (CFP->getValueAPF().isInfinity()) {
1747  if (CFP->getValueAPF().isNegative()) {
1748  if (Cond == ISD::SETOEQ &&
1749  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1751  if (Cond == ISD::SETUEQ &&
1752  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1754  if (Cond == ISD::SETUNE &&
1755  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1757  if (Cond == ISD::SETONE &&
1758  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1760  } else {
1761  if (Cond == ISD::SETOEQ &&
1762  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1764  if (Cond == ISD::SETUEQ &&
1765  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1767  if (Cond == ISD::SETUNE &&
1768  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1770  if (Cond == ISD::SETONE &&
1771  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1773  }
1774  }
1775  }
1776  }
1777 
1778  if (N0 == N1) {
1779  // The sext(setcc()) => setcc() optimization relies on the appropriate
1780  // constant being emitted.
1781  uint64_t EqVal = 0;
1782  switch (getBooleanContents(N0.getValueType())) {
1785  EqVal = ISD::isTrueWhenEqual(Cond);
1786  break;
1788  EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1789  break;
1790  }
1791 
1792  // We can always fold X == X for integer setcc's.
1793  if (N0.getValueType().isInteger()) {
1794  return DAG.getConstant(EqVal, VT);
1795  }
1796  unsigned UOF = ISD::getUnorderedFlavor(Cond);
1797  if (UOF == 2) // FP operators that are undefined on NaNs.
1798  return DAG.getConstant(EqVal, VT);
1799  if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1800  return DAG.getConstant(EqVal, VT);
1801  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1802  // if it is not already.
1803  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1804  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1805  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1806  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1807  }
1808 
1809  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1810  N0.getValueType().isInteger()) {
1811  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812  N0.getOpcode() == ISD::XOR) {
1813  // Simplify (X+Y) == (X+Z) --> Y == Z
1814  if (N0.getOpcode() == N1.getOpcode()) {
1815  if (N0.getOperand(0) == N1.getOperand(0))
1816  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1817  if (N0.getOperand(1) == N1.getOperand(1))
1818  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1819  if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1820  // If X op Y == Y op X, try other combinations.
1821  if (N0.getOperand(0) == N1.getOperand(1))
1822  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1823  Cond);
1824  if (N0.getOperand(1) == N1.getOperand(0))
1825  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1826  Cond);
1827  }
1828  }
1829 
1830  // If RHS is a legal immediate value for a compare instruction, we need
1831  // to be careful about increasing register pressure needlessly.
1832  bool LegalRHSImm = false;
1833 
1834  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1835  if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1836  // Turn (X+C1) == C2 --> X == C2-C1
1837  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1838  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1839  DAG.getConstant(RHSC->getAPIntValue()-
1840  LHSR->getAPIntValue(),
1841  N0.getValueType()), Cond);
1842  }
1843 
1844  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1845  if (N0.getOpcode() == ISD::XOR)
1846  // If we know that all of the inverted bits are zero, don't bother
1847  // performing the inversion.
1848  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1849  return
1850  DAG.getSetCC(dl, VT, N0.getOperand(0),
1851  DAG.getConstant(LHSR->getAPIntValue() ^
1852  RHSC->getAPIntValue(),
1853  N0.getValueType()),
1854  Cond);
1855  }
1856 
1857  // Turn (C1-X) == C2 --> X == C1-C2
1858  if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1859  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1860  return
1861  DAG.getSetCC(dl, VT, N0.getOperand(1),
1862  DAG.getConstant(SUBC->getAPIntValue() -
1863  RHSC->getAPIntValue(),
1864  N0.getValueType()),
1865  Cond);
1866  }
1867  }
1868 
1869  // Could RHSC fold directly into a compare?
1870  if (RHSC->getValueType(0).getSizeInBits() <= 64)
1871  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1872  }
1873 
1874  // Simplify (X+Z) == X --> Z == 0
1875  // Don't do this if X is an immediate that can fold into a cmp
1876  // instruction and X+Z has other uses. It could be an induction variable
1877  // chain, and the transform would increase register pressure.
1878  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1879  if (N0.getOperand(0) == N1)
1880  return DAG.getSetCC(dl, VT, N0.getOperand(1),
1881  DAG.getConstant(0, N0.getValueType()), Cond);
1882  if (N0.getOperand(1) == N1) {
1883  if (DAG.isCommutativeBinOp(N0.getOpcode()))
1884  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885  DAG.getConstant(0, N0.getValueType()), Cond);
1886  if (N0.getNode()->hasOneUse()) {
1887  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1888  // (Z-X) == X --> Z == X<<1
1889  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1890  DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1891  if (!DCI.isCalledByLegalizer())
1892  DCI.AddToWorklist(SH.getNode());
1893  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1894  }
1895  }
1896  }
1897  }
1898 
1899  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1900  N1.getOpcode() == ISD::XOR) {
1901  // Simplify X == (X+Z) --> Z == 0
1902  if (N1.getOperand(0) == N0)
1903  return DAG.getSetCC(dl, VT, N1.getOperand(1),
1904  DAG.getConstant(0, N1.getValueType()), Cond);
1905  if (N1.getOperand(1) == N0) {
1906  if (DAG.isCommutativeBinOp(N1.getOpcode()))
1907  return DAG.getSetCC(dl, VT, N1.getOperand(0),
1908  DAG.getConstant(0, N1.getValueType()), Cond);
1909  if (N1.getNode()->hasOneUse()) {
1910  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1911  // X == (Z-X) --> X<<1 == Z
1912  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1913  DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1914  if (!DCI.isCalledByLegalizer())
1915  DCI.AddToWorklist(SH.getNode());
1916  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1917  }
1918  }
1919  }
1920 
1921  // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1922  // Note that where y is variable and is known to have at most
1923  // one bit set (for example, if it is z&1) we cannot do this;
1924  // the expressions are not equivalent when y==0.
1925  if (N0.getOpcode() == ISD::AND)
1926  if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1927  if (ValueHasExactlyOneBitSet(N1, DAG)) {
1928  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1929  if (DCI.isBeforeLegalizeOps() ||
1930  isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1931  SDValue Zero = DAG.getConstant(0, N1.getValueType());
1932  return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1933  }
1934  }
1935  }
1936  if (N1.getOpcode() == ISD::AND)
1937  if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1938  if (ValueHasExactlyOneBitSet(N0, DAG)) {
1939  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1940  if (DCI.isBeforeLegalizeOps() ||
1941  isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1942  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1943  return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1944  }
1945  }
1946  }
1947  }
1948 
1949  // Fold away ALL boolean setcc's.
1950  SDValue Temp;
1951  if (N0.getValueType() == MVT::i1 && foldBooleans) {
1952  switch (Cond) {
1953  default: llvm_unreachable("Unknown integer setcc!");
1954  case ISD::SETEQ: // X == Y -> ~(X^Y)
1955  Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1956  N0 = DAG.getNOT(dl, Temp, MVT::i1);
1957  if (!DCI.isCalledByLegalizer())
1958  DCI.AddToWorklist(Temp.getNode());
1959  break;
1960  case ISD::SETNE: // X != Y --> (X^Y)
1961  N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1962  break;
1963  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1964  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1965  Temp = DAG.getNOT(dl, N0, MVT::i1);
1966  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1967  if (!DCI.isCalledByLegalizer())
1968  DCI.AddToWorklist(Temp.getNode());
1969  break;
1970  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1971  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1972  Temp = DAG.getNOT(dl, N1, MVT::i1);
1973  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1974  if (!DCI.isCalledByLegalizer())
1975  DCI.AddToWorklist(Temp.getNode());
1976  break;
1977  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1978  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1979  Temp = DAG.getNOT(dl, N0, MVT::i1);
1980  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1981  if (!DCI.isCalledByLegalizer())
1982  DCI.AddToWorklist(Temp.getNode());
1983  break;
1984  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1985  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1986  Temp = DAG.getNOT(dl, N1, MVT::i1);
1987  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1988  break;
1989  }
1990  if (VT != MVT::i1) {
1991  if (!DCI.isCalledByLegalizer())
1992  DCI.AddToWorklist(N0.getNode());
1993  // FIXME: If running after legalize, we probably can't do this.
1994  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1995  }
1996  return N0;
1997  }
1998 
1999  // Could not fold it.
2000  return SDValue();
2001 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned Log2_32_Ceil(uint32_t Value)
Definition: MathExtras.h:465
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
bool hasOneUse() const
bool hasOneUse() const
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
bool isUnindexed() const
isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
virtual bool isLegalICmpImmediate(int64_t) const
unsigned getValueSizeInBits() const
const SDValue & getOperand(unsigned Num) const
static bool isCommutativeBinOp(unsigned Opcode)
bool isTrueWhenEqual(CondCode Cond)
Definition: ISDOpcodes.h:809
const SDValue & getBasePtr() const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:421
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
EVT getShiftAmountTy(EVT LHSTy) const
bool isLittleEndian() const
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:166
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
EVT getValueType(unsigned ResNo) const
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
MachinePointerInfo getWithOffset(int64_t O) const
virtual MVT getPointerTy(uint32_t=0) const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
bool isSignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:796
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:196
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
SDNode * getNode() const
get the SDNode which holds the desired result
bool isTypeLegal(EVT VT) const
assert(Globals.size() > 1)
const SDValue & getOperand(unsigned i) const
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1314
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
const DataLayout * getDataLayout() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
unsigned getOpcode() const
unsigned getUnorderedFlavor(CondCode Cond)
Definition: ISDOpcodes.h:817
CondCode getSetCCSwappedOperands(CondCode Operation)
bool isVolatile() const
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
const MachinePointerInfo & getPointerInfo() const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:178
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
const SDValue & getChain() const
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
Definition: APInt.h:428
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:452
ISD::LoadExtType getExtensionType() const
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
Definition: APInt.h:416
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
uint64_t MinAlign(uint64_t A, uint64_t B)
Definition: MathExtras.h:544
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
unsigned countTrailingOnes() const
Count the number of trailing one bits.
Definition: APInt.h:1378
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
FoldSetCC - Constant fold a setcc to true or false.
EVT getValueType() const
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:431
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
BooleanContent
Enum that describes how the target represents true/false values.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void TargetLowering::softenSetCCOperands ( SelectionDAG DAG,
EVT  VT,
SDValue NewLHS,
SDValue NewRHS,
ISD::CondCode CCCode,
SDLoc  dl 
) const
inherited

SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 117 of file TargetLowering.cpp.

120  {
121  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122  && "Unsupported setcc type!");
123 
124  // Expand into one or more soft-fp libcall(s).
126  switch (CCCode) {
127  case ISD::SETEQ:
128  case ISD::SETOEQ:
129  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
131  break;
132  case ISD::SETNE:
133  case ISD::SETUNE:
134  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
136  break;
137  case ISD::SETGE:
138  case ISD::SETOGE:
139  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
141  break;
142  case ISD::SETLT:
143  case ISD::SETOLT:
144  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
146  break;
147  case ISD::SETLE:
148  case ISD::SETOLE:
149  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
151  break;
152  case ISD::SETGT:
153  case ISD::SETOGT:
154  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
156  break;
157  case ISD::SETUO:
158  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
160  break;
161  case ISD::SETO:
162  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163  (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
164  break;
165  default:
166  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
168  switch (CCCode) {
169  case ISD::SETONE:
170  // SETONE = SETOLT | SETOGT
171  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
173  // Fallthrough
174  case ISD::SETUGT:
175  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
177  break;
178  case ISD::SETUGE:
179  LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
181  break;
182  case ISD::SETULT:
183  LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
185  break;
186  case ISD::SETULE:
187  LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
189  break;
190  case ISD::SETUEQ:
191  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
193  break;
194  default: llvm_unreachable("Do not know how to soften this setcc!");
195  }
196  }
197 
198  // Use the target specific return value for comparions lib calls.
199  EVT RetVT = getCmpLibcallReturnType();
200  SDValue Ops[2] = { NewLHS, NewRHS };
201  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
202  dl).first;
203  NewRHS = DAG.getConstant(0, RetVT);
204  CCCode = getCmpLibcallCC(LC1);
205  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206  SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207  getSetCCResultType(*DAG.getContext(), RetVT),
208  NewLHS, NewRHS, DAG.getCondCode(CCCode));
209  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
210  dl).first;
211  NewLHS = DAG.getNode(ISD::SETCC, dl,
212  getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213  NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
215  NewRHS = SDValue();
216  }
217 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
assert(Globals.size() > 1)
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
EVT getValueType() const
SDValue getCondCode(ISD::CondCode Cond)
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
bool llvm::TargetLoweringBase::supportJumpTables ( ) const
inlineinherited

Return whether the target can generate code for jump tables.

Definition at line 827 of file TargetLowering.h.

827  {
828  return SupportJumpTables;
829  }
CCAssignFn * PPCTargetLowering::useFastISelCCs ( unsigned  Flag) const
private

Definition at line 2107 of file PPCISelLowering.cpp.

2107  {
2108  return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2109 }
bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inlineinherited

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 822 of file TargetLowering.h.

822  {
823  return UseUnderscoreLongJmp;
824  }
bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inlineinherited

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 817 of file TargetLowering.h.

817  {
818  return UseUnderscoreSetJmp;
819  }
bool TargetLowering::verifyReturnAddressArgumentIsConstant ( SDValue  Op,
SelectionDAG DAG 
) const
inherited

Definition at line 2772 of file TargetLowering.cpp.

2772  {
2773  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2774  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2775  "be a constant integer");
2776  return true;
2777  }
2778 
2779  return false;
2780 }
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
void emitError(unsigned LocCookie, const Twine &ErrorStr)
const SDValue & getOperand(unsigned i) const

Field Documentation

bool llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal
protectedinherited

MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.

Definition at line 1842 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protectedinherited

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 1814 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protectedinherited

Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute.

Definition at line 1818 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protectedinherited

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 1830 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protectedinherited

Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.

Definition at line 1834 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protectedinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 1797 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protectedinherited

Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.

Definition at line 1801 of file TargetLowering.h.

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protectedinherited

Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Definition at line 1838 of file TargetLowering.h.

const PPCSubtarget& llvm::PPCTargetLowering::Subtarget
private

Definition at line 345 of file PPCISelLowering.h.


The documentation for this class was generated from the following files: